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293a62dabe
litex
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verilog
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m1crg
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Sebastien Bourdeauducq
c86dd3cbef
Define clock domains instead of passing extra clocks as regular signals
2012-09-11 00:21:07 +02:00
..
m1crg.v
Define clock domains instead of passing extra clocks as regular signals
2012-09-11 00:21:07 +02:00