73 lines
2.7 KiB
Plaintext
73 lines
2.7 KiB
Plaintext
[> 2020.XX, planned for July 2020
|
|
---------------------------------
|
|
|
|
[> Issues resolved
|
|
------------------
|
|
- Fix flush_cpu_icache on VexRiscv.
|
|
- Fix `.data` section placed in rom (#566)
|
|
|
|
[> Added Features
|
|
------------------
|
|
- Properly integrate Minerva CPU.
|
|
- Add nMigen dependency.
|
|
- Pluggable CPUs.
|
|
- BIOS history, autocomplete.
|
|
- Improve boards's programmers.
|
|
- Add Microwatt CPU support (with GHDL-Yosys-plugin support for FOSS toolchains).
|
|
- Speedup Memtest using an LFSR.
|
|
- Add LedChaser on boards.
|
|
- Improve WishboneBridge.
|
|
- Improve Diamond constraints.
|
|
- Use InterconnectPointToPoint when 1 master,1 slave and no address translation.
|
|
- Add CV32E40P CPU support (ex RI5CY).
|
|
- JTAG UART with uart_name=jtag_uart (validated on Spartan6, 7-Series, Ultrascale(+)).
|
|
- Add Symbiflow experimental support on Arty.
|
|
- Add SDCard (SPI and SD modes) boot from FAT/exFAT filesystems with FatFs.
|
|
- Simplify boot with boot.json configuration file.
|
|
- Revert to a single crt0 (avoid ctr/xip variants).
|
|
- Add otional DMA bus for Cache Coherency on CPU(s) with DMA/Cache Coherency interface.
|
|
- Add AXI-Lite bus standard support.
|
|
|
|
[> API changes/Deprecation
|
|
--------------------------
|
|
- Add --build --load arguments to targets.
|
|
- Deprecate soc.interconnect.wishbone.UpConverter (will be rewritten if useful).
|
|
- Deprecate soc.interconnect.wishbone.CSRBank (Does not seem to be used by anyone).
|
|
- Move soc.interconnect.wishbone2csr.WB2CSR to soc.interconnect.wishbone.Wishbone2CSR.
|
|
- Move soc.interconnect.wishbonebridge.WishboneStreamingBridge to soc.cores.uart.Stream2Wishbone.
|
|
- Rename --gateware-toolchain target parameter to --toolchain.
|
|
- Integrate Zynq's PS7 as a regular CPU (zynq7000) and deprecate SoCZynq.
|
|
|
|
[> 2020.04, released April 28th, 2020
|
|
-------------------------------------
|
|
|
|
[> Description
|
|
--------------
|
|
First release of LiteX and the ecosystem of cores!
|
|
|
|
LiteX is a Migen/MiSoC based Core/SoC builder that provides the infrastructure to easily create
|
|
Cores/SoCs (with or without CPU).
|
|
|
|
The common components of a SoC are provided directly:
|
|
- Buses and Streams (Wishbone, AXI, Avalon-ST)
|
|
- Interconnect
|
|
- Common cores (RAM, ROM, Timer, UART, etc...)
|
|
- CPU wrappers/integration
|
|
- etc...
|
|
And SoC creation capabilities can be greatly extended with the ecosystem of LiteX cores (DRAM,
|
|
PCIe, Ethernet, SATA, etc...) that can be integrated/simulated/build easily with LiteX.
|
|
|
|
It also provides build backends for open-source and vendors toolchains.
|
|
|
|
[> Issues resolved
|
|
------------------
|
|
- NA
|
|
|
|
[> Added Features
|
|
------------------
|
|
- NA
|
|
|
|
[> API changes/Deprecation
|
|
--------------------------
|
|
- https://github.com/enjoy-digital/litex/pull/399: Converting LiteX to use Python modules.
|