53 lines
1.8 KiB
Python
Executable File
53 lines
1.8 KiB
Python
Executable File
#!/usr/bin/env python3
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from setuptools import setup
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from setuptools import find_packages
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setup(
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name="litex",
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description="Python SoC/Core builder for building FPGA based systems.",
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author="Florent Kermarrec",
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author_email="florent@enjoy-digital.fr",
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url="http://enjoy-digital.fr",
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download_url="https://github.com/enjoy-digital/litex",
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test_suite="test",
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license="BSD",
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python_requires="~=3.6",
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install_requires=[
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"migen",
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"pyserial",
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"requests",
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"pythondata-software-compiler_rt",
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],
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packages=find_packages(exclude=("test*", "sim*", "doc*")),
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include_package_data=True,
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platforms=["Any"],
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keywords="HDL ASIC FPGA hardware design",
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classifiers=[
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"Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)",
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"Environment :: Console",
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"Development Status :: Alpha",
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"Intended Audience :: Developers",
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"License :: OSI Approved :: BSD License",
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"Operating System :: OS Independent",
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"Programming Language :: Python",
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],
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entry_points={
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"console_scripts": [
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# full names
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"litex_term=litex.tools.litex_term:main",
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"litex_server=litex.tools.litex_server:main",
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"litex_jtag_uart=litex.tools.litex_jtag_uart:main",
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"litex_crossover_uart=litex.tools.litex_crossover_uart:main",
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"litex_sim=litex.tools.litex_sim:main",
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"litex_read_verilog=litex.tools.litex_read_verilog:main",
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"litex_simple=litex.boards.targets.simple:main",
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# short names
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"lxterm=litex.tools.litex_term:main",
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"lxserver=litex.tools.litex_server:main",
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"lxsim=litex.tools.litex_sim:main",
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],
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},
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)
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