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litex/litex/gen
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Florent Kermarrec 9c890a0a27 gen/fhdl/verilog: Simplify/Rename registers initialization parameter.
2023-05-17 17:24:06 +02:00
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fhdl gen/fhdl/verilog: Simplify/Rename registers initialization parameter. 2023-05-17 17:24:06 +02:00
sim
__init__.py litex/gen: Move LiteXModule to gen/fhdl/module.py. 2022-10-28 19:38:24 +02:00
common.py gen/common: Add Unsigned/Signed Signal wrappers. 2023-02-28 10:17:16 +01:00