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litex/migen/fhdl
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Sébastien Bourdeauducq 2a4cc3875c Merge pull request #6 from larsclausen/master 
Minor improvements
2013-03-17 07:33:14 -07:00
..
__init__.py Initial import, FHDL basic structure, divider example 2011-12-04 16:44:38 +01:00
module.py Make ClockDomains part of fragments 2013-03-15 18:17:33 +01:00
namer.py New 'specials' API 2013-02-22 17:56:35 +01:00
specials.py fhdl/specials: fix rename_clock_domain declarations 2013-03-15 19:47:01 +01:00
structure.py Merge pull request #6 from larsclausen/master 2013-03-17 07:33:14 -07:00
tools.py Make ClockDomains part of fragments 2013-03-15 18:17:33 +01:00
tracer.py bank: automatic register naming 2013-03-12 15:45:24 +01:00
verilog.py Make ClockDomains part of fragments 2013-03-15 18:17:33 +01:00
visit.py fhdl: support nested statement lists 2013-01-05 14:18:15 +01:00