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2ad83778bf
litex
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litex
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Florent Kermarrec
2ad83778bf
bios: allow testing main_ram at init when using an external controller
2018-11-26 15:21:00 +01:00
..
boards
platforms/avalanche: add IOStandard on ddram pins
2018-11-23 12:47:45 +01:00
build
build/microsemi/libero_soc: small cleanup
2018-11-26 11:35:06 +01:00
gen
gen: add common with reverse_bits/reverse_bytes functions
2018-10-30 10:15:29 +01:00
soc
bios: allow testing main_ram at init when using an external controller
2018-11-26 15:21:00 +01:00
utils
utils/litex_read_verilog: fix generated indent on instance
2018-11-22 17:33:46 +01:00
__init__.py
ease RemoteClient import
2018-09-23 10:23:00 +02:00