58 lines
2.0 KiB
ReStructuredText
58 lines
2.0 KiB
ReStructuredText
.. _about-litesata:
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================
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About LiteSATA
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================
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LiteSATA provides a small footprint and configurable SATA1/2/3 core.
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LiteSATA is part of LiteX libraries whose aims is to lower entry level of complex
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FPGA IP cores by providing simple, elegant and efficient implementations of
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components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
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The core uses simple and specific streaming buses and will provides in the future
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adapters to use standardized AXI or Avalon-ST streaming buses.
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Since Python is used to describe the HDL, the core is highly and easily
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configurable.
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The synthetizable BIST can be used as a starting point to integrate SATA in
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your own SoC.
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LiteSATA uses technologies developed in partnership with M-Labs Ltd:
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- Migen enables generating HDL with Python in an efficient way.
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- MiSoC provides the basic blocks to build a powerful and small footprint SoC.
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LiteSATA can be used as a Migen/MiSoC library (by simply installing it
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with the provided setup.py) or can be integrated with your standard design flow
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by generating the verilog rtl that you will use as a standard core.
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.. _about-litesata-toolchain:
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Features
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====================
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PHY:
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- OOB, COMWAKE, COMINIT
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- ALIGN inserter/remover and bytes alignment on K28.5
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- 8B/10B encoding/decoding in transceiver
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- Errors detection and reporting
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- 32 bits interface
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- 1.5/3.0/6.0GBps supported speeds (respectively 37.5/75/150MHz system clk)
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Core:
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Link:
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- CONT inserter/remover
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- Scrambling/Descrambling of data
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- CRC inserter/checker
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- HOLD insertion/detection
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- Errors detection and reporting
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Transport/Command:
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- Easy to use user interfaces (Can be used with or without CPU)
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- 48 bits sector addressing
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- 3 supported commands: READ_DMA(_EXT), WRITE_DMA(_EXT), IDENTIFY_DEVICE
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- Errors detection and reporting
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Frontend:
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- Configurable crossbar (simply use core.crossbar.get_port() to add a new port!)
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- Ports arbitration transparent to the user
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- Synthetizable BIST
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