Sean Cross 2d75aee7e0 soc_core: ctrl: document registers ... This adds a small amount of documentation to the three registers present inside the `CTRL` module. Signed-off-by: Sean Cross <sean@xobs.io>		2020-01-02 15:37:45 +08:00
..
cores	cores: timer: fix documentation formatting	2020-01-02 15:36:35 +08:00
integration	soc_core: ctrl: document registers	2020-01-02 15:37:45 +08:00
interconnect	soc/interconnect/csr: add fields support for CSRStorage's write simulation method	2019-12-02 09:44:44 +01:00
software	moving RAM offsets outside of CSR_ETHMAC define	2019-12-29 22:56:42 -08:00
__init__.py	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00