litex/litex
Florent Kermarrec 2ed5f14e9e integration/soc/soc_core: Remove --min-l2-data-width and --max-sdram-size that don't need to be configurable but can just be enforced in the target file. 2021-03-29 11:26:29 +02:00
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build lattice: use pnmainc on windows 2021-03-27 04:36:02 -07:00
compat compat/stream_sim: Remove TODO since will not be done. 2021-03-24 17:58:13 +01:00
gen gen/fhdl/verilog: improve clock domain error reporting. 2020-11-10 13:27:29 +01:00
soc integration/soc/soc_core: Remove --min-l2-data-width and --max-sdram-size that don't need to be configurable but can just be enforced in the target file. 2021-03-29 11:26:29 +02:00
tools tools/litex_json2dts: Fix i2c node 2021-03-28 12:44:45 +02:00
__init__.py revert get_data_mod change (Vexrisv SMP repo has been renamed to pythondata-cpu-vexriscv_smp). 2020-11-05 19:55:18 +01:00