Jiaxun Yang 1e21105731 test/test_integration: Add test for various bus options ... Test bus standard/data-width/address-width/interconnect combinations. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>		2024-12-20 12:22:39 +00:00
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__init__.py	add test directory with test_code_8b10b.py (from misoc)	2017-04-24 18:46:55 +02:00
test_avalon_mm.py
test_axi.py	soc/test: Make data_width/address_width/addressing explicit on Wishbone.Interface calls.	2023-10-27 10:55:13 +02:00
test_axi_lite.py
test_axi_stream.py
test_bitbang.py
test_clock.py
test_code_8b10b.py
test_csr.py
test_ecc.py
test_emif.py
test_fifosyncmacro.py
test_gearbox.py
test_hyperbus.py
test_i2c.py
test_i2s.py	test: add SPDX License identifier to header and specify file is part of LiteX.	2020-08-23 15:40:21 +02:00
test_icap.py
test_integration.py
test_led.py
test_packet.py
test_prbs.py
test_reduce.py
test_spi.py	test: add SPDX License identifier to header and specify file is part of LiteX.	2020-08-23 15:40:21 +02:00
test_spi_mmap.py
test_spi_opi.py	test: add SPDX License identifier to header and specify file is part of LiteX.	2020-08-23 15:40:21 +02:00
test_stream.py
test_timer.py	test/test_timer: Update.	2021-05-27 19:37:51 +02:00
test_wishbone.py