80 lines
2.4 KiB
Python
80 lines
2.4 KiB
Python
from migen.fhdl.std import *
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from migen.genlib.cdc import MultiReg
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from migen.bank.description import *
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class Clocking(Module, AutoCSR):
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def __init__(self, pads):
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self._r_pll_reset = CSRStorage(reset=1)
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self._r_locked = CSRStatus()
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# DRP
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self._r_pll_adr = CSRStorage(5)
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self._r_pll_dat_r = CSRStatus(16)
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self._r_pll_dat_w = CSRStorage(16)
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self._r_pll_read = CSR()
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self._r_pll_write = CSR()
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self._r_pll_drdy = CSRStatus()
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self.locked = Signal()
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self.serdesstrobe = Signal()
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self.clock_domains._cd_pix = ClockDomain()
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self.clock_domains._cd_pix2x = ClockDomain()
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self.clock_domains._cd_pix10x = ClockDomain(reset_less=True)
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###
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clk_se = Signal()
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self.specials += Instance("IBUFDS", i_I=pads.clk_p, i_IB=pads.clk_n, o_O=clk_se)
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clkfbout = Signal()
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pll_locked = Signal()
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pll_clk0 = Signal()
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pll_clk1 = Signal()
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pll_clk2 = Signal()
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pll_drdy = Signal()
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self.sync += If(self._r_pll_read.re | self._r_pll_write.re,
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self._r_pll_drdy.status.eq(0)
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).Elif(pll_drdy,
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self._r_pll_drdy.status.eq(1)
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)
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self.specials += Instance("PLL_ADV",
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p_CLKFBOUT_MULT=10,
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p_CLKOUT0_DIVIDE=1, # pix10x
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p_CLKOUT1_DIVIDE=5, # pix2x
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p_CLKOUT2_DIVIDE=10, # pix
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p_COMPENSATION="INTERNAL",
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i_CLKINSEL=1,
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i_CLKIN1=clk_se,
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o_CLKOUT0=pll_clk0, o_CLKOUT1=pll_clk1, o_CLKOUT2=pll_clk2,
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o_CLKFBOUT=clkfbout, i_CLKFBIN=clkfbout,
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o_LOCKED=pll_locked, i_RST=self._r_pll_reset.storage,
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i_DADDR=self._r_pll_adr.storage,
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o_DO=self._r_pll_dat_r.status,
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i_DI=self._r_pll_dat_w.storage,
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i_DEN=self._r_pll_read.re | self._r_pll_write.re,
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i_DWE=self._r_pll_write.re,
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o_DRDY=pll_drdy,
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i_DCLK=ClockSignal())
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locked_async = Signal()
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self.specials += [
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Instance("BUFPLL", p_DIVIDE=5,
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i_PLLIN=pll_clk0, i_GCLK=ClockSignal("pix2x"), i_LOCKED=pll_locked,
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o_IOCLK=self._cd_pix10x.clk, o_LOCK=locked_async, o_SERDESSTROBE=self.serdesstrobe),
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Instance("BUFG", i_I=pll_clk1, o_O=self._cd_pix2x.clk),
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Instance("BUFG", i_I=pll_clk2, o_O=self._cd_pix.clk),
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MultiReg(locked_async, self.locked, "sys")
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]
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self.comb += self._r_locked.status.eq(self.locked)
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# sychronize pix+pix2x reset
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pix_rst_n = 1
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for i in range(2):
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new_pix_rst_n = Signal()
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self.specials += Instance("FDCE", i_D=pix_rst_n, i_CE=1, i_C=ClockSignal("pix"),
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i_CLR=~locked_async, o_Q=new_pix_rst_n)
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pix_rst_n = new_pix_rst_n
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self.comb += self._cd_pix.rst.eq(~pix_rst_n), self._cd_pix2x.rst.eq(~pix_rst_n)
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