47 lines
1.5 KiB
Python
47 lines
1.5 KiB
Python
from migen.fhdl.std import *
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from migen.genlib.fifo import AsyncFIFO
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from migen.genlib.record import layout_len
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from migen.bank.description import AutoCSR
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from migen.actorlib import structuring, dma_lasmi, spi
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from misoclib.dvisampler.edid import EDID
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from misoclib.dvisampler.clocking import Clocking
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from misoclib.dvisampler.datacapture import DataCapture
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class RawDVISampler(Module, AutoCSR):
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def __init__(self, pads, asmiport):
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self.submodules.edid = EDID(pads)
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self.submodules.clocking = Clocking(pads)
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invert = False
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try:
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s = getattr(pads, "data0")
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except AttributeError:
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s = getattr(pads, "data0_n")
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invert = True
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self.submodules.data0_cap = DataCapture(8, invert)
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self.comb += [
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self.data0_cap.pad.eq(s),
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self.data0_cap.serdesstrobe.eq(self.clocking.serdesstrobe)
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]
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fifo = RenameClockDomains(AsyncFIFO(10, 256),
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{"write": "pix", "read": "sys"})
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self.submodules += fifo
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self.comb += [
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fifo.din.eq(self.data0_cap.d),
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fifo.we.eq(1)
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]
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pack_factor = asmiport.hub.dw//16
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self.submodules.packer = structuring.Pack([("word", 10), ("pad", 6)], pack_factor)
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self.submodules.cast = structuring.Cast(self.packer.source.payload.layout, asmiport.hub.dw)
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self.submodules.dma = spi.DMAWriteController(dma_lasmi.Writer(lasmim), spi.MODE_SINGLE_SHOT)
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self.comb += [
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self.packer.sink.stb.eq(fifo.readable),
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fifo.re.eq(self.packer.sink.ack),
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self.packer.sink.payload.word.eq(fifo.dout),
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self.packer.source.connect_flat(self.cast.sink),
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self.cast.source.connect_flat(self.dma.data)
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]
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