141 lines
4.4 KiB
Python
141 lines
4.4 KiB
Python
from migen.fhdl.std import *
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from migen.genlib.fsm import FSM, NextState
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from migen.bank.description import *
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from migen.bank.eventmanager import *
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from migen.flow.actor import *
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from migen.actorlib import dma_lasmi
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# Slot status: EMPTY=0 LOADED=1 PENDING=2
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class _Slot(Module, AutoCSR):
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def __init__(self, addr_bits, alignment_bits):
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self.ev_source = EventSourceLevel()
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self.address = Signal(addr_bits)
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self.address_reached = Signal(addr_bits)
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self.address_valid = Signal()
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self.address_done = Signal()
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self._r_status = CSRStorage(2, write_from_dev=True)
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self._r_address = CSRStorage(addr_bits + alignment_bits, alignment_bits=alignment_bits, write_from_dev=True)
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###
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self.comb += [
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self.address.eq(self._r_address.storage),
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self.address_valid.eq(self._r_status.storage[0]),
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self._r_status.dat_w.eq(2),
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self._r_status.we.eq(self.address_done),
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self._r_address.dat_w.eq(self.address_reached),
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self._r_address.we.eq(self.address_done),
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self.ev_source.trigger.eq(self._r_status.storage[1])
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]
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class _SlotArray(Module, AutoCSR):
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def __init__(self, nslots, addr_bits, alignment_bits):
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self.submodules.ev = EventManager()
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self.address = Signal(addr_bits)
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self.address_reached = Signal(addr_bits)
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self.address_valid = Signal()
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self.address_done = Signal()
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###
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slots = [_Slot(addr_bits, alignment_bits) for i in range(nslots)]
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for n, slot in enumerate(slots):
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setattr(self.submodules, "slot"+str(n), slot)
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setattr(self.ev, "slot"+str(n), slot.ev_source)
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self.ev.finalize()
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change_slot = Signal()
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current_slot = Signal(max=nslots)
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self.sync += If(change_slot, [If(slot.address_valid, current_slot.eq(n)) for n, slot in reversed(list(enumerate(slots)))])
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self.comb += change_slot.eq(~self.address_valid | self.address_done)
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self.comb += [
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self.address.eq(Array(slot.address for slot in slots)[current_slot]),
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self.address_valid.eq(Array(slot.address_valid for slot in slots)[current_slot])
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]
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self.comb += [slot.address_reached.eq(self.address_reached) for slot in slots]
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self.comb += [slot.address_done.eq(self.address_done & (current_slot == n)) for n, slot in enumerate(slots)]
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class DMA(Module):
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def __init__(self, lasmim, nslots):
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bus_aw = lasmim.aw
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bus_dw = lasmim.dw
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alignment_bits = bits_for(bus_dw//8) - 1
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fifo_word_width = 24*bus_dw//32
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self.frame = Sink([("sof", 1), ("pixels", fifo_word_width)])
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self._r_frame_size = CSRStorage(bus_aw + alignment_bits, alignment_bits=alignment_bits)
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self.submodules._slot_array = _SlotArray(nslots, bus_aw, alignment_bits)
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self.ev = self._slot_array.ev
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###
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# address generator + maximum memory word count to prevent DMA buffer overrun
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reset_words = Signal()
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count_word = Signal()
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last_word = Signal()
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current_address = Signal(bus_aw)
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mwords_remaining = Signal(bus_aw)
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self.comb += [
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self._slot_array.address_reached.eq(current_address),
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last_word.eq(mwords_remaining == 1)
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]
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self.sync += [
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If(reset_words,
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current_address.eq(self._slot_array.address),
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mwords_remaining.eq(self._r_frame_size.storage)
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).Elif(count_word,
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current_address.eq(current_address + 1),
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mwords_remaining.eq(mwords_remaining - 1)
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)
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]
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# 24bpp -> 32bpp
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memory_word = Signal(bus_dw)
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pixbits = []
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for i in range(bus_dw//32):
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for j in range(3):
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b = (i*3+j)*8
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pixbits.append(self.frame.payload.pixels[b+6:b+8])
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pixbits.append(self.frame.payload.pixels[b:b+8])
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pixbits.append(0)
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pixbits.append(0)
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self.comb += memory_word.eq(Cat(*pixbits))
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# bus accessor
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self.submodules._bus_accessor = dma_lasmi.Writer(lasmim)
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self.comb += [
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self._bus_accessor.address_data.payload.a.eq(current_address),
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self._bus_accessor.address_data.payload.d.eq(memory_word)
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]
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# control FSM
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fsm = FSM()
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self.submodules += fsm
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fsm.act("WAIT_SOF",
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reset_words.eq(1),
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self.frame.ack.eq(~self._slot_array.address_valid | ~self.frame.payload.sof),
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If(self._slot_array.address_valid & self.frame.payload.sof & self.frame.stb, NextState("TRANSFER_PIXELS"))
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)
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fsm.act("TRANSFER_PIXELS",
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self.frame.ack.eq(self._bus_accessor.address_data.ack),
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If(self.frame.stb,
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self._bus_accessor.address_data.stb.eq(1),
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If(self._bus_accessor.address_data.ack,
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count_word.eq(1),
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If(last_word, NextState("EOF"))
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)
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)
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)
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fsm.act("EOF",
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If(~self._bus_accessor.busy,
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self._slot_array.address_done.eq(1),
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NextState("WAIT_SOF")
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)
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)
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def get_csrs(self):
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return [self._r_frame_size] + self._slot_array.get_csrs()
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