190 lines
4.6 KiB
Python
190 lines
4.6 KiB
Python
from migen.fhdl.std import *
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from migen.fhdl.specials import Tristate
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from migen.genlib.cdc import MultiReg
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from migen.genlib.fsm import FSM, NextState
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from migen.genlib.misc import chooser
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from migen.bank.description import CSRStorage, CSRStatus, AutoCSR
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_default_edid = [
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0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x3D, 0x17, 0x32, 0x12, 0x2A, 0x6A, 0xBF, 0x00,
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0x05, 0x17, 0x01, 0x03, 0x80, 0x28, 0x1E, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x2E, 0x00, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
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0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0xB2, 0x0C, 0x00, 0x40, 0x41, 0x00, 0x26, 0x30, 0x18, 0x88,
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0x36, 0x00, 0x28, 0x1E, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x4D, 0x31, 0x20,
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0x44, 0x56, 0x49, 0x20, 0x6D, 0x69, 0x78, 0x65, 0x72, 0x0A, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x34,
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]
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class EDID(Module, AutoCSR):
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def __init__(self, pads, default=_default_edid):
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self._r_hpd_notif = CSRStatus()
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self._r_hpd_en = CSRStorage()
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self.specials.mem = Memory(8, 128, init=default)
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###
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# HPD
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if hasattr(pads, "hpd_notif"):
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self.specials += MultiReg(pads.hpd_notif, self._r_hpd_notif.status)
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else:
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self.comb += self._r_hpd_notif.status.eq(1)
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if hasattr(pads, "hpd_en"):
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self.comb += pads.hpd_en.eq(self._r_hpd_en.storage)
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# EDID
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scl_raw = Signal()
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sda_i = Signal()
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sda_drv = Signal()
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_sda_drv_reg = Signal()
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_sda_i_async = Signal()
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self.sync += _sda_drv_reg.eq(sda_drv)
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self.specials += [
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MultiReg(pads.scl, scl_raw),
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Tristate(pads.sda, 0, _sda_drv_reg, _sda_i_async),
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MultiReg(_sda_i_async, sda_i)
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]
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scl_i = Signal()
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samp_count = Signal(6)
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samp_carry = Signal()
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self.sync += [
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Cat(samp_count, samp_carry).eq(samp_count + 1),
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If(samp_carry, scl_i.eq(scl_raw))
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]
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scl_r = Signal()
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sda_r = Signal()
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scl_rising = Signal()
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sda_rising = Signal()
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sda_falling = Signal()
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self.sync += [
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scl_r.eq(scl_i),
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sda_r.eq(sda_i)
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]
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self.comb += [
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scl_rising.eq(scl_i & ~scl_r),
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sda_rising.eq(sda_i & ~sda_r),
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sda_falling.eq(~sda_i & sda_r)
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]
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start = Signal()
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self.comb += start.eq(scl_i & sda_falling)
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din = Signal(8)
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counter = Signal(max=9)
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self.sync += [
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If(start, counter.eq(0)),
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If(scl_rising,
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If(counter == 8,
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counter.eq(0)
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).Else(
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counter.eq(counter + 1),
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din.eq(Cat(sda_i, din[:7]))
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)
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)
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]
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is_read = Signal()
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update_is_read = Signal()
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self.sync += If(update_is_read, is_read.eq(din[0]))
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offset_counter = Signal(max=128)
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oc_load = Signal()
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oc_inc = Signal()
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self.sync += [
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If(oc_load,
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offset_counter.eq(din)
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).Elif(oc_inc,
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offset_counter.eq(offset_counter + 1)
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)
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]
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rdport = self.mem.get_port()
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self.specials += rdport
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self.comb += rdport.adr.eq(offset_counter)
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data_bit = Signal()
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zero_drv = Signal()
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data_drv = Signal()
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self.comb += If(zero_drv, sda_drv.eq(1)).Elif(data_drv, sda_drv.eq(~data_bit))
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data_drv_en = Signal()
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data_drv_stop = Signal()
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self.sync += If(data_drv_en, data_drv.eq(1)).Elif(data_drv_stop, data_drv.eq(0))
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self.sync += If(data_drv_en, chooser(rdport.dat_r, counter, data_bit, 8, reverse=True))
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fsm = FSM()
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self.submodules += fsm
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fsm.act("WAIT_START")
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fsm.act("RCV_ADDRESS",
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If(counter == 8,
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If(din[1:] == 0x50,
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update_is_read.eq(1),
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NextState("ACK_ADDRESS0")
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).Else(
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NextState("WAIT_START")
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)
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)
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)
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fsm.act("ACK_ADDRESS0",
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If(~scl_i, NextState("ACK_ADDRESS1"))
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)
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fsm.act("ACK_ADDRESS1",
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zero_drv.eq(1),
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If(scl_i, NextState("ACK_ADDRESS2"))
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)
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fsm.act("ACK_ADDRESS2",
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zero_drv.eq(1),
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If(~scl_i,
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If(is_read,
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NextState("READ")
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).Else(
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NextState("RCV_OFFSET")
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)
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)
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)
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fsm.act("RCV_OFFSET",
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If(counter == 8,
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oc_load.eq(1),
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NextState("ACK_OFFSET0")
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)
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)
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fsm.act("ACK_OFFSET0",
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If(~scl_i, NextState("ACK_OFFSET1"))
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)
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fsm.act("ACK_OFFSET1",
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zero_drv.eq(1),
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If(scl_i, NextState("ACK_OFFSET2"))
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)
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fsm.act("ACK_OFFSET2",
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zero_drv.eq(1),
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If(~scl_i, NextState("RCV_ADDRESS"))
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)
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fsm.act("READ",
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If(~scl_i,
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If(counter == 8,
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data_drv_stop.eq(1),
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NextState("ACK_READ")
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).Else(
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data_drv_en.eq(1)
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)
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)
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)
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fsm.act("ACK_READ",
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If(scl_rising,
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oc_inc.eq(1),
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If(sda_i,
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NextState("WAIT_START")
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).Else(
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NextState("READ")
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)
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)
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)
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for state in fsm.actions.keys():
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fsm.act(state, If(start, NextState("RCV_ADDRESS")))
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fsm.act(state, If(~self._r_hpd_en.storage, NextState("WAIT_START")))
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