60 lines
1.8 KiB
Python
60 lines
1.8 KiB
Python
from migen.fhdl.std import *
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from migen.bank.description import *
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from migen.genlib.misc import optree
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from migen.genlib.cdc import PulseSynchronizer
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from misoclib.dvisampler.common import control_tokens
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class WER(Module, AutoCSR):
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def __init__(self, period_bits=24):
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self.data = Signal(10)
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self._r_update = CSR()
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self._r_value = CSRStatus(period_bits)
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###
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# pipeline stage 1
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# we ignore the 10th (inversion) bit, as it is independent of the transition minimization
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data_r = Signal(9)
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self.sync.pix += data_r.eq(self.data[:9])
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# pipeline stage 2
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transitions = Signal(8)
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self.comb += [transitions[i].eq(data_r[i] ^ data_r[i+1]) for i in range(8)]
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transition_count = Signal(max=9)
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self.sync.pix += transition_count.eq(optree("+", [transitions[i] for i in range(8)]))
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is_control = Signal()
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self.sync.pix += is_control.eq(optree("|", [data_r == ct for ct in control_tokens]))
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# pipeline stage 3
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is_error = Signal()
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self.sync.pix += is_error.eq((transition_count > 4) & ~is_control)
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# counter
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period_counter = Signal(period_bits)
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period_done = Signal()
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self.sync.pix += Cat(period_counter, period_done).eq(period_counter + 1)
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wer_counter = Signal(period_bits)
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wer_counter_r = Signal(period_bits)
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wer_counter_r_updated = Signal()
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self.sync.pix += [
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wer_counter_r_updated.eq(period_done),
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If(period_done,
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wer_counter_r.eq(wer_counter),
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wer_counter.eq(0)
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).Elif(is_error,
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wer_counter.eq(wer_counter + 1)
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)
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]
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# sync to system clock domain
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wer_counter_sys = Signal(period_bits)
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self.submodules.ps_counter = PulseSynchronizer("pix", "sys")
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self.comb += self.ps_counter.i.eq(wer_counter_r_updated)
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self.sync += If(self.ps_counter.o, wer_counter_sys.eq(wer_counter_r))
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# register interface
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self.sync += If(self._r_update.re, self._r_value.status.eq(wer_counter_sys))
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