220 lines
6.6 KiB
Python
220 lines
6.6 KiB
Python
from migen.fhdl.std import *
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from migen.genlib.fifo import AsyncFIFO
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from migen.genlib.cdc import MultiReg
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from migen.bank.description import *
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from migen.flow.actor import *
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from misoclib.framebuffer.format import bpc_phy, phy_layout
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from misoclib.framebuffer import dvi
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class _FIFO(Module):
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def __init__(self, pack_factor):
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self.phy = Sink(phy_layout(pack_factor))
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self.busy = Signal()
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self.pix_hsync = Signal()
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self.pix_vsync = Signal()
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self.pix_de = Signal()
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self.pix_r = Signal(bpc_phy)
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self.pix_g = Signal(bpc_phy)
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self.pix_b = Signal(bpc_phy)
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###
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fifo = RenameClockDomains(AsyncFIFO(phy_layout(pack_factor), 512),
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{"write": "sys", "read": "pix"})
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self.submodules += fifo
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self.comb += [
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self.phy.ack.eq(fifo.writable),
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fifo.we.eq(self.phy.stb),
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fifo.din.eq(self.phy.payload),
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self.busy.eq(0)
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]
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unpack_counter = Signal(max=pack_factor)
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assert(pack_factor & (pack_factor - 1) == 0) # only support powers of 2
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self.sync.pix += [
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unpack_counter.eq(unpack_counter + 1),
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self.pix_hsync.eq(fifo.dout.hsync),
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self.pix_vsync.eq(fifo.dout.vsync),
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self.pix_de.eq(fifo.dout.de)
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]
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for i in range(pack_factor):
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pixel = getattr(fifo.dout, "p"+str(i))
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self.sync.pix += If(unpack_counter == i,
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self.pix_r.eq(pixel.r),
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self.pix_g.eq(pixel.g),
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self.pix_b.eq(pixel.b)
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)
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self.comb += fifo.re.eq(unpack_counter == (pack_factor - 1))
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# This assumes a 50MHz base clock
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class _Clocking(Module, AutoCSR):
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def __init__(self, pads_vga, pads_dvi):
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self._r_cmd_data = CSRStorage(10)
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self._r_send_cmd_data = CSR()
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self._r_send_go = CSR()
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self._r_status = CSRStatus(4)
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self.clock_domains.cd_pix = ClockDomain(reset_less=True)
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if pads_dvi is not None:
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self._r_pll_reset = CSRStorage()
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self._r_pll_adr = CSRStorage(5)
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self._r_pll_dat_r = CSRStatus(16)
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self._r_pll_dat_w = CSRStorage(16)
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self._r_pll_read = CSR()
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self._r_pll_write = CSR()
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self._r_pll_drdy = CSRStatus()
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self.clock_domains.cd_pix2x = ClockDomain(reset_less=True)
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self.clock_domains.cd_pix10x = ClockDomain(reset_less=True)
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self.serdesstrobe = Signal()
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###
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# Generate 1x pixel clock
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clk_pix_unbuffered = Signal()
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pix_progdata = Signal()
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pix_progen = Signal()
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pix_progdone = Signal()
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pix_locked = Signal()
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self.specials += Instance("DCM_CLKGEN",
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p_CLKFXDV_DIVIDE=2, p_CLKFX_DIVIDE=4, p_CLKFX_MD_MAX=1.0, p_CLKFX_MULTIPLY=2,
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p_CLKIN_PERIOD=20.0, p_SPREAD_SPECTRUM="NONE", p_STARTUP_WAIT="FALSE",
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i_CLKIN=ClockSignal("base50"), o_CLKFX=clk_pix_unbuffered,
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i_PROGCLK=ClockSignal(), i_PROGDATA=pix_progdata, i_PROGEN=pix_progen,
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o_PROGDONE=pix_progdone, o_LOCKED=pix_locked,
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i_FREEZEDCM=0, i_RST=ResetSignal())
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remaining_bits = Signal(max=11)
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transmitting = Signal()
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self.comb += transmitting.eq(remaining_bits != 0)
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sr = Signal(10)
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self.sync += [
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If(self._r_send_cmd_data.re,
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remaining_bits.eq(10),
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sr.eq(self._r_cmd_data.storage)
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).Elif(transmitting,
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remaining_bits.eq(remaining_bits - 1),
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sr.eq(sr[1:])
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)
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]
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self.comb += [
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pix_progdata.eq(transmitting & sr[0]),
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pix_progen.eq(transmitting | self._r_send_go.re)
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]
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# enforce gap between commands
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busy_counter = Signal(max=14)
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busy = Signal()
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self.comb += busy.eq(busy_counter != 0)
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self.sync += If(self._r_send_cmd_data.re,
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busy_counter.eq(13)
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).Elif(busy,
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busy_counter.eq(busy_counter - 1)
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)
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mult_locked = Signal()
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self.comb += self._r_status.status.eq(Cat(busy, pix_progdone, pix_locked, mult_locked))
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# Clock multiplication and buffering
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if pads_dvi is None:
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# Just buffer 1x pixel clock
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self.specials += Instance("BUFG", i_I=clk_pix_unbuffered, o_O=self.cd_pix.clk)
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self.comb += mult_locked.eq(pix_locked)
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else:
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# Route unbuffered 1x pixel clock to PLL
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# Generate 1x, 2x and 10x IO pixel clocks
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clkfbout = Signal()
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pll_locked = Signal()
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pll_clk0 = Signal()
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pll_clk1 = Signal()
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pll_clk2 = Signal()
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locked_async = Signal()
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pll_drdy = Signal()
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self.sync += If(self._r_pll_read.re | self._r_pll_write.re,
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self._r_pll_drdy.status.eq(0)
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).Elif(pll_drdy,
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self._r_pll_drdy.status.eq(1)
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)
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self.specials += [
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Instance("PLL_ADV",
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p_CLKFBOUT_MULT=10,
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p_CLKOUT0_DIVIDE=1, # pix10x
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p_CLKOUT1_DIVIDE=5, # pix2x
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p_CLKOUT2_DIVIDE=10, # pix
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p_COMPENSATION="INTERNAL",
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i_CLKINSEL=1,
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i_CLKIN1=clk_pix_unbuffered,
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o_CLKOUT0=pll_clk0, o_CLKOUT1=pll_clk1, o_CLKOUT2=pll_clk2,
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o_CLKFBOUT=clkfbout, i_CLKFBIN=clkfbout,
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o_LOCKED=pll_locked,
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i_RST=~pix_locked | self._r_pll_reset.storage,
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i_DADDR=self._r_pll_adr.storage,
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o_DO=self._r_pll_dat_r.status,
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i_DI=self._r_pll_dat_w.storage,
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i_DEN=self._r_pll_read.re | self._r_pll_write.re,
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i_DWE=self._r_pll_write.re,
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o_DRDY=pll_drdy,
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i_DCLK=ClockSignal()),
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Instance("BUFPLL", p_DIVIDE=5,
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i_PLLIN=pll_clk0, i_GCLK=ClockSignal("pix2x"), i_LOCKED=pll_locked,
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o_IOCLK=self.cd_pix10x.clk, o_LOCK=locked_async, o_SERDESSTROBE=self.serdesstrobe),
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Instance("BUFG", i_I=pll_clk1, o_O=self.cd_pix2x.clk),
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Instance("BUFG", name="dviout_pix_bufg", i_I=pll_clk2, o_O=self.cd_pix.clk),
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MultiReg(locked_async, mult_locked, "sys")
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]
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# Drive VGA/DVI clock pads
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if pads_vga is not None:
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self.specials += Instance("ODDR2",
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p_DDR_ALIGNMENT="NONE", p_INIT=0, p_SRTYPE="SYNC",
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o_Q=pads_vga.clk,
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i_C0=ClockSignal("pix"),
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i_C1=~ClockSignal("pix"),
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i_CE=1, i_D0=1, i_D1=0,
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i_R=0, i_S=0)
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if pads_dvi is not None:
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dvi_clk_se = Signal()
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self.specials += Instance("ODDR2",
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p_DDR_ALIGNMENT="NONE", p_INIT=0, p_SRTYPE="SYNC",
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o_Q=dvi_clk_se,
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i_C0=ClockSignal("pix"),
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i_C1=~ClockSignal("pix"),
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i_CE=1, i_D0=1, i_D1=0,
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i_R=0, i_S=0)
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self.specials += Instance("OBUFDS", i_I=dvi_clk_se,
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o_O=pads_dvi.clk_p, o_OB=pads_dvi.clk_n)
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class Driver(Module, AutoCSR):
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def __init__(self, pack_factor, pads_vga, pads_dvi):
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fifo = _FIFO(pack_factor)
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self.submodules += fifo
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self.phy = fifo.phy
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self.busy = fifo.busy
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self.submodules.clocking = _Clocking(pads_vga, pads_dvi)
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if pads_vga is not None:
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self.comb += [
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pads_vga.hsync_n.eq(~fifo.pix_hsync),
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pads_vga.vsync_n.eq(~fifo.pix_vsync),
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pads_vga.r.eq(fifo.pix_r),
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pads_vga.g.eq(fifo.pix_g),
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pads_vga.b.eq(fifo.pix_b),
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pads_vga.psave_n.eq(1)
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]
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if pads_dvi is not None:
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self.submodules.dvi_phy = dvi.PHY(self.clocking.serdesstrobe, pads_dvi)
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self.comb += [
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self.dvi_phy.hsync.eq(fifo.pix_hsync),
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self.dvi_phy.vsync.eq(fifo.pix_vsync),
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self.dvi_phy.de.eq(fifo.pix_de),
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self.dvi_phy.r.eq(fifo.pix_r),
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self.dvi_phy.g.eq(fifo.pix_g),
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self.dvi_phy.b.eq(fifo.pix_b)
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]
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