42 lines
1.1 KiB
Python
42 lines
1.1 KiB
Python
from migen.fhdl.std import *
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from migen.bus.lasmibus import *
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from migen.sim.generic import run_simulation
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from misoclib.lasmicon.bankmachine import *
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from common import sdram_phy, sdram_geom, sdram_timing, CommandLogger
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def my_generator():
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for x in range(10):
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yield True, x
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for x in range(10):
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yield False, 128*x
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class TB(Module):
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def __init__(self):
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self.req = Interface(32, 32, 1,
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sdram_timing.req_queue_size, sdram_phy.read_latency, sdram_phy.write_latency)
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self.submodules.dut = BankMachine(sdram_geom, sdram_timing, 2, 0, self.req)
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self.submodules.logger = CommandLogger(self.dut.cmd, True)
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self.generator = my_generator()
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self.dat_ack_cnt = 0
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def do_simulation(self, selfp):
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if selfp.req.dat_ack:
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self.dat_ack_cnt += 1
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if selfp.req.req_ack:
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try:
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we, adr = next(self.generator)
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except StopIteration:
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selfp.req.stb = 0
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if not selfp.req.lock:
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print("data ack count: {0}".format(self.dat_ack_cnt))
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raise StopSimulation
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return
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selfp.req.adr = adr
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selfp.req.we = we
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selfp.req.stb = 1
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if __name__ == "__main__":
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run_simulation(TB(), vcd_name="my.vcd")
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