113 lines
2.8 KiB
Python
113 lines
2.8 KiB
Python
from migen.fhdl.std import *
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from migen.genlib.misc import optree
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from migen.bank.description import *
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from migen.actorlib import dma_lasmi
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from migen.actorlib.spi import *
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@DecorateModule(InsertReset)
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@DecorateModule(InsertCE)
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class LFSR(Module):
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def __init__(self, n_out, n_state=31, taps=[27, 30]):
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self.o = Signal(n_out)
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###
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state = Signal(n_state)
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curval = [state[i] for i in range(n_state)]
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curval += [0]*(n_out - n_state)
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for i in range(n_out):
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nv = ~optree("^", [curval[tap] for tap in taps])
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curval.insert(0, nv)
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curval.pop()
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self.sync += [
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state.eq(Cat(*curval[:n_state])),
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self.o.eq(Cat(*curval))
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]
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memtest_magic = 0x361f
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class MemtestWriter(Module):
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def __init__(self, lasmim):
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self._r_magic = CSRStatus(16)
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self._r_reset = CSR()
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self._r_shoot = CSR()
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self.submodules._dma = DMAWriteController(dma_lasmi.Writer(lasmim), MODE_EXTERNAL)
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###
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self.comb += self._r_magic.status.eq(memtest_magic)
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lfsr = LFSR(lasmim.dw)
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self.submodules += lfsr
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self.comb += lfsr.reset.eq(self._r_reset.re)
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en = Signal()
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en_counter = Signal(lasmim.aw)
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self.comb += en.eq(en_counter != 0)
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self.sync += [
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If(self._r_shoot.re,
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en_counter.eq(self._dma.length)
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).Elif(lfsr.ce,
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en_counter.eq(en_counter - 1)
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)
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]
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self.comb += [
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self._dma.trigger.eq(self._r_shoot.re),
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self._dma.data.stb.eq(en),
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lfsr.ce.eq(en & self._dma.data.ack),
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self._dma.data.payload.d.eq(lfsr.o)
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]
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def get_csrs(self):
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return [self._r_magic, self._r_reset, self._r_shoot] + self._dma.get_csrs()
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class MemtestReader(Module):
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def __init__(self, lasmim):
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self._r_magic = CSRStatus(16)
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self._r_reset = CSR()
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self._r_error_count = CSRStatus(lasmim.aw)
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self.submodules._dma = DMAReadController(dma_lasmi.Reader(lasmim), MODE_SINGLE_SHOT)
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###
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self.comb += self._r_magic.status.eq(memtest_magic)
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lfsr = LFSR(lasmim.dw)
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self.submodules += lfsr
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self.comb += lfsr.reset.eq(self._r_reset.re)
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self.comb += [
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lfsr.ce.eq(self._dma.data.stb),
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self._dma.data.ack.eq(1)
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]
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err_cnt = self._r_error_count.status
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self.sync += [
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If(self._r_reset.re,
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err_cnt.eq(0)
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).Elif(self._dma.data.stb,
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If(self._dma.data.payload.d != lfsr.o, err_cnt.eq(err_cnt + 1))
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)
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]
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def get_csrs(self):
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return [self._r_magic, self._r_reset, self._r_error_count] + self._dma.get_csrs()
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class _LFSRTB(Module):
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def __init__(self, *args, **kwargs):
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self.submodules.dut = LFSR(*args, **kwargs)
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self.comb += self.dut.ce.eq(1)
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def do_simulation(self, selfp):
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print("{0:032x}".format(selfp.dut.o))
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if __name__ == "__main__":
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from migen.fhdl import verilog
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from migen.sim.generic import run_simulation
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lfsr = LFSR(3, 4, [3, 2])
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print(verilog.convert(lfsr, ios={lfsr.ce, lfsr.reset, lfsr.o}))
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run_simulation(_LFSRTB(128), ncycles=20)
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