103 lines
2.1 KiB
Python
103 lines
2.1 KiB
Python
from migen.fhdl.std import *
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from migen.bus import wishbone
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from migen.genlib.fsm import FSM, NextState
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class NorFlash16(Module):
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def __init__(self, pads, rd_timing, wr_timing):
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self.bus = wishbone.Interface()
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###
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data = TSTriple(16)
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lsb = Signal()
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self.specials += data.get_tristate(pads.d)
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self.comb += [
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data.oe.eq(pads.oe_n),
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pads.ce_n.eq(0)
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]
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load_lo = Signal()
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load_hi = Signal()
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store = Signal()
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pads.oe_n.reset, pads.we_n.reset = 1, 1
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self.sync += [
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pads.oe_n.eq(1),
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pads.we_n.eq(1),
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# Register data/address to avoid off-chip glitches
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If(self.bus.cyc & self.bus.stb,
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pads.adr.eq(Cat(lsb, self.bus.adr)),
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If(self.bus.we,
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# Only 16-bit writes are supported. Assume sel=0011 or 1100.
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If(self.bus.sel[0],
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data.o.eq(self.bus.dat_w[:16])
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).Else(
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data.o.eq(self.bus.dat_w[16:])
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)
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).Else(
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pads.oe_n.eq(0)
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)
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),
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If(load_lo, self.bus.dat_r[:16].eq(data.i)),
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If(load_hi, self.bus.dat_r[16:].eq(data.i)),
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If(store, pads.we_n.eq(0))
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]
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# Typical timing of the flash chips:
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# - 110ns address to output
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# - 50ns write pulse width
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counter = Signal(max=max(rd_timing, wr_timing)+1)
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counter_en = Signal()
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counter_wr_mode = Signal()
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counter_done = Signal()
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self.comb += counter_done.eq(counter == Mux(counter_wr_mode, wr_timing, rd_timing))
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self.sync += If(counter_en & ~counter_done,
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counter.eq(counter + 1)
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).Else(
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counter.eq(0)
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)
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fsm = FSM()
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self.submodules += fsm
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fsm.act("IDLE",
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If(self.bus.cyc & self.bus.stb,
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If(self.bus.we,
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NextState("WR")
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).Else(
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NextState("RD_HI")
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)
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)
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)
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fsm.act("RD_HI",
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lsb.eq(0),
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counter_en.eq(1),
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If(counter_done,
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load_hi.eq(1),
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NextState("RD_LO")
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)
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)
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fsm.act("RD_LO",
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lsb.eq(1),
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counter_en.eq(1),
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If(counter_done,
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load_lo.eq(1),
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NextState("ACK")
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)
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)
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fsm.act("WR",
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# supported cases: sel=0011 [lsb=1] and sel=1100 [lsb=0]
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lsb.eq(self.bus.sel[0]),
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counter_wr_mode.eq(1),
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counter_en.eq(1),
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store.eq(1),
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If(counter_done, NextState("ACK"))
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)
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fsm.act("ACK",
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self.bus.ack.eq(1),
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NextState("IDLE")
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)
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