243 lines
6.3 KiB
Python
243 lines
6.3 KiB
Python
from math import ceil
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from migen.fhdl.std import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.genlib.fsm import FSM, NextState
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from lib.sata.k7sataphy.std import *
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class K7SATAPHYReconfig(Module):
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def __init__(self, channel_drp, mmcm_drp):
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self.speed = Signal(3)
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###
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speed_r = Signal(3)
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speed_change = Signal()
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self.sync += speed_r.eq(self.speed)
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self.comb += speed_change.eq(self.speed != speed_r)
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drp_sel = Signal()
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drp = DRPBus()
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self.comb += \
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If(drp_sel,
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drp.connect(mmcm_drp)
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).Else(
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drp.connect(channel_drp)
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)
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class K7SATAPHYCRG(Module):
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def __init__(self, pads, gtx, clk_freq, default_speed):
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self.reset = Signal()
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self.ready = Signal()
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self.clock_domains.cd_sata_tx = ClockDomain()
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self.clock_domains.cd_sata_rx = ClockDomain()
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# CPLL
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# (SATA3) 150MHz / VCO @ 3GHz / Line rate @ 6Gbps
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# (SATA2 & SATA1) VCO still @ 3 GHz, Line rate is decreased with output divivers.
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# When changing rate, reconfiguration of the CPLL over DRP is needed to:
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# - update the output divider
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# - update the equalizer configuration (specific for each line rate).
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refclk = Signal()
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self.specials += Instance("IBUFDS_GTE2",
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i_CEB=0,
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i_I=pads.refclk_p,
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i_IB=pads.refclk_n,
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o_O=refclk
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)
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self.comb += gtx.gtrefclk0.eq(refclk)
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# TX clocking
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# (SATA3) 150MHz from CPLL TXOUTCLK, sata_tx clk @ 300MHz (16-bits)
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# (SATA2) 150MHz from CPLL TXOUTCLK, sata_tx clk @ 150MHz (16-bits)
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# (SATA1) 150MHz from CPLL TXOUTCLK, sata_tx clk @ 75MHz (16-bits)
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# When changing rate, reconfiguration of the MMCM is needed to update the output divider.
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mmcm_reset = Signal()
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mmcm_locked = Signal()
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mmcm_drp = DRPBus()
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mmcm_fb = Signal()
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mmcm_clk_i = Signal()
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mmcm_clk0_o = Signal()
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mmcm_clk1_o = Signal()
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mmcm_div_config = {
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"SATA1" : 16,
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"SATA2" : 8,
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"SATA3" : 4
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}
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mmcm_div = mmcm_div_config[default_speed]
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self.specials += [
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Instance("BUFG", i_I=gtx.txoutclk, o_O=mmcm_clk_i),
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Instance("MMCME2_ADV",
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p_BANDWIDTH="HIGH", p_COMPENSATION="ZHOLD", i_RST=mmcm_reset, o_LOCKED=mmcm_locked,
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# DRP
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i_DCLK=mmcm_drp.clk, i_DEN=mmcm_drp.en, o_DRDY=mmcm_drp.rdy, i_DWE=mmcm_drp.we,
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i_DADDR=mmcm_drp.addr, i_DI=mmcm_drp.di, o_DO=mmcm_drp.do,
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# VCO
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p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=6.666,
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p_CLKFBOUT_MULT_F=8.000, p_CLKFBOUT_PHASE=0.000, p_DIVCLK_DIVIDE=1,
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i_CLKIN1=mmcm_clk_i, i_CLKFBIN=mmcm_fb, o_CLKFBOUT=mmcm_fb,
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# CLK0
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p_CLKOUT0_DIVIDE_F=mmcm_div, p_CLKOUT0_PHASE=0.000, o_CLKOUT0=mmcm_clk0_o,
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# CLK1
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p_CLKOUT1_DIVIDE=mmcm_div*2, p_CLKOUT1_PHASE=0.000, o_CLKOUT1=mmcm_clk1_o,
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),
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Instance("BUFG", i_I=mmcm_clk0_o, o_O=self.cd_sata_tx.clk),
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]
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self.comb += [
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gtx.txusrclk.eq(self.cd_sata_tx.clk),
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gtx.txusrclk2.eq(self.cd_sata_tx.clk)
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]
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# RX clocking
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# (SATA3) sata_rx recovered clk @ 300MHz from CPLL RXOUTCLK
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# (SATA2) sata_rx recovered clk @ 150MHz from CPLL RXOUTCLK
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# (SATA1) sata_rx recovered clk @ 150MHz from CPLL RXOUTCLK
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self.specials += [
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Instance("BUFG", i_I=gtx.rxoutclk, o_O=self.cd_sata_rx.clk),
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]
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self.comb += [
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gtx.rxusrclk.eq(self.cd_sata_rx.clk),
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gtx.rxusrclk2.eq(self.cd_sata_rx.clk)
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]
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# Bypass TX buffer
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self.comb += [
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gtx.txphdlyreset.eq(0),
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gtx.txphalignen.eq(0),
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gtx.txdlyen.eq(0),
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gtx.txphalign.eq(0),
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gtx.txphinit.eq(0)
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]
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# Bypass RX buffer
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self.comb += [
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gtx.rxphdlyreset.eq(0),
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gtx.rxdlyen.eq(0),
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gtx.rxphalign.eq(0),
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gtx.rxphalignen.eq(0),
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]
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# Configuration Reset
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# After configuration, GTX resets have to stay low for at least 500ns
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# See AR43482
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reset_en = Signal()
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clk_period_ns = 1000000000/clk_freq
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reset_en_cnt_max = ceil(500/clk_period_ns)
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reset_en_cnt = Signal(max=reset_en_cnt_max, reset=reset_en_cnt_max-1)
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self.sync += If(~reset_en, reset_en_cnt.eq(reset_en_cnt-1))
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self.comb += reset_en.eq(reset_en_cnt == 0)
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# TX Reset FSM
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tx_reset_fsm = FSM(reset_state="IDLE")
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self.submodules += tx_reset_fsm
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tx_reset_fsm.act("IDLE",
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gtx.txuserrdy.eq(0),
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gtx.gttxreset.eq(0),
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gtx.txdlysreset.eq(0),
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If(reset_en,
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NextState("RESET_ALL"),
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)
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)
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tx_reset_fsm.act("RESET_ALL",
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gtx.txuserrdy.eq(0),
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gtx.gttxreset.eq(1),
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gtx.txdlysreset.eq(1),
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If(gtx.cplllock & mmcm_locked,
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NextState("RELEASE_GTXRESET")
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)
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)
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tx_reset_fsm.act("RELEASE_GTXRESET",
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gtx.txuserrdy.eq(1),
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gtx.gttxreset.eq(0),
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gtx.txdlysreset.eq(1),
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If(self.reset,
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NextState("RESET_ALL")
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).Elif(gtx.txresetdone,
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NextState("RELEASE_DLYRESET")
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)
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)
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tx_reset_fsm.act("RELEASE_DLYRESET",
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gtx.txuserrdy.eq(1),
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gtx.gttxreset.eq(0),
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gtx.txdlysreset.eq(0),
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If(self.reset,
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NextState("RESET_ALL")
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).Elif(gtx.txdlysresetdone,
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NextState("READY")
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)
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)
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tx_reset_fsm.act("READY",
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gtx.txuserrdy.eq(1),
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gtx.gttxreset.eq(0),
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gtx.txdlysreset.eq(0),
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If(self.reset,
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NextState("RESET_ALL")
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)
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)
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# RX Reset FSM
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rx_reset_fsm = FSM(reset_state="IDLE")
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self.submodules += rx_reset_fsm
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rx_reset_fsm.act("IDLE",
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gtx.rxuserrdy.eq(0),
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gtx.gtrxreset.eq(0),
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gtx.rxdlysreset.eq(0),
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If(reset_en,
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NextState("RESET_ALL"),
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)
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)
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rx_reset_fsm.act("RESET_ALL",
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gtx.rxuserrdy.eq(0),
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gtx.gtrxreset.eq(1),
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gtx.rxdlysreset.eq(1),
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If(gtx.cplllock & mmcm_locked,
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NextState("RELEASE_GTXRESET")
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)
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)
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rx_reset_fsm.act("RELEASE_GTXRESET",
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gtx.rxuserrdy.eq(1),
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gtx.gtrxreset.eq(0),
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gtx.rxdlysreset.eq(1),
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If(self.reset,
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NextState("RESET_ALL")
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).Elif(gtx.rxresetdone,
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NextState("RELEASE_DLYRESET")
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)
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)
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rx_reset_fsm.act("RELEASE_DLYRESET",
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gtx.rxuserrdy.eq(1),
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gtx.gtrxreset.eq(0),
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gtx.rxdlysreset.eq(0),
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If(self.reset,
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NextState("RESET_ALL")
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).Elif(gtx.rxdlysresetdone,
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NextState("READY")
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)
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)
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rx_reset_fsm.act("READY",
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gtx.rxuserrdy.eq(1),
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gtx.gtrxreset.eq(0),
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gtx.rxdlysreset.eq(0),
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If(self.reset,
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NextState("RESET_ALL")
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)
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)
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self.comb += self.ready.eq(tx_reset_fsm.ongoing("READY") & rx_reset_fsm.ongoing("READY"))
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# Reset PLL
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self.comb += gtx.cpllreset.eq(self.reset | ~reset_en)
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# Reset for SATA TX/RX clock domains
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self.specials += [
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AsyncResetSynchronizer(self.cd_sata_tx, ~self.ready),
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AsyncResetSynchronizer(self.cd_sata_rx, ~self.ready),
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]
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# Dynamic Reconfiguration
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self.submodules.reconfig = K7SATAPHYReconfig(mmcm_drp, gtx.drp)
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