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litex/miscope
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Florent Kermarrec 2fb418a373 use new MiSoC UART with phase accumulators 
this will allow to speed up MiLa reads
 		2014-09-24 21:56:15 +02:00
..
host uart2wishbone: disconnect rx line from shared pads when bridge is selected 2014-08-03 13:15:56 +02:00
__init__.py - reworking WIP 2013-02-22 16:40:49 +01:00
miio.py clean up 2014-08-03 11:44:27 +02:00
mila.py use verilog namespace to export mila configuration 2014-08-03 17:09:01 +02:00
std.py clean up 2014-08-03 11:44:27 +02:00
storage.py clean up 2014-08-03 11:44:27 +02:00
trigger.py clean up 2014-08-03 11:44:27 +02:00
uart2wishbone.py use new MiSoC UART with phase accumulators 2014-09-24 21:56:15 +02:00