litex/litex
Florent Kermarrec 3022f02b3f build/xilinx/vivado: update add_period_constraint behavior when clock is already constrainted. 2019-12-31 10:32:09 +01:00
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boards platforms/netv2: add xc7a100t support 2019-12-17 09:47:31 +01:00
build build/xilinx/vivado: update add_period_constraint behavior when clock is already constrainted. 2019-12-31 10:32:09 +01:00
gen Add integer attributes 2019-12-19 09:03:12 +01:00
soc soc/integration/builder: avoid try/except on LiteDRAM import, just check if SoC has an sdram and do the import if so 2019-12-31 09:58:26 +01:00
tools tools/remote/comm_udp: only use one socket 2019-11-22 15:28:35 +01:00
__init__.py soc/interconnect: rename stream_packet to packet & cleanup (with retro-compat) 2019-09-30 23:41:07 +02:00