145 lines
4.2 KiB
Python
145 lines
4.2 KiB
Python
from migen import *
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from migen.genlib.misc import timeline
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from misoc.interconnect import wishbone
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from misoc.interconnect.csr import AutoCSR, CSRStorage, CSRStatus
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_FAST_READ = 0x0b
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_DIOFR = 0xbb
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_QIOFR = 0xeb
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def _format_cmd(cmd, spi_width):
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"""
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`cmd` is the read instruction. Since everything is transmitted on all
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dq lines (cmd, adr and data), extend/interleave cmd to full pads.dq
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width even if dq1-dq3 are don't care during the command phase:
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For example, for N25Q128, 0xeb is the quad i/o fast read, and
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extended to 4 bits (dq1,dq2,dq3 high) is: 0xfffefeff
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"""
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c = 2**(8*spi_width)-1
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for b in range(8):
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if not (cmd>>b)%2:
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c &= ~(1<<(b*spi_width))
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return c
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class SpiFlash(Module, AutoCSR):
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def __init__(self, pads, dummy=15, div=2, with_bitbang=True):
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"""
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Simple SPI flash, e.g. N25Q128 on the LX9 Microboard.
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Supports multi-bit pseudo-parallel reads (aka Dual or Quad I/O Fast
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Read). Only supports mode0 (cpol=0, cpha=0).
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Optionally supports software bitbanging (for write, erase, or other commands).
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"""
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self.bus = bus = wishbone.Interface()
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spi_width = len(pads.dq)
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if with_bitbang:
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self.bitbang = CSRStorage(4)
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self.miso = CSRStatus()
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self.bitbang_en = CSRStorage()
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###
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cs_n = Signal(reset=1)
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clk = Signal()
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dq_oe = Signal()
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wbone_width = len(bus.dat_r)
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read_cmd_params = {
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4: (_format_cmd(_QIOFR, 4), 4*8),
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2: (_format_cmd(_DIOFR, 2), 2*8),
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1: (_format_cmd(_FAST_READ, 1), 1*8)
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}
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read_cmd, cmd_width = read_cmd_params[spi_width]
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addr_width = 24
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pads.cs_n.reset = 1
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dq = TSTriple(spi_width)
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self.specials.dq = dq.get_tristate(pads.dq)
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sr = Signal(max(cmd_width, addr_width, wbone_width))
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dqs = Replicate(1, spi_width-1)
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self.comb += bus.dat_r.eq(sr)
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hw_read_logic = [
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pads.clk.eq(clk),
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pads.cs_n.eq(cs_n),
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dq.o.eq(sr[-spi_width:]),
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dq.oe.eq(dq_oe)
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]
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if with_bitbang:
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bitbang_logic = [
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pads.clk.eq(self.bitbang.storage[1]),
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pads.cs_n.eq(self.bitbang.storage[2]),
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dq.o.eq(Cat(self.bitbang.storage[0], dqs)),
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If(self.bitbang.storage[3],
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dq.oe.eq(0)
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).Else(
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dq.oe.eq(1)
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),
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If(self.bitbang.storage[1],
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self.miso.status.eq(dq.i[1])
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)
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]
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self.comb += \
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If(self.bitbang_en.storage,
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bitbang_logic
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).Else(
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hw_read_logic
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)
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else:
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self.comb += hw_read_logic
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if div < 2:
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raise ValueError("Unsupported value \'{}\' for div parameter for SpiFlash core".format(div))
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else:
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i = Signal(max=div)
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dqi = Signal(spi_width)
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self.sync += [
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If(i == div//2 - 1,
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clk.eq(1),
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dqi.eq(dq.i),
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),
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If(i == div - 1,
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i.eq(0),
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clk.eq(0),
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sr.eq(Cat(dqi, sr[:-spi_width]))
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).Else(
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i.eq(i + 1),
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),
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]
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# spi is byte-addressed, prefix by zeros
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z = Replicate(0, log2_int(wbone_width//8))
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seq = [
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(cmd_width//spi_width*div,
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[dq_oe.eq(1), cs_n.eq(0), sr[-cmd_width:].eq(read_cmd)]),
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(addr_width//spi_width*div,
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[sr[-addr_width:].eq(Cat(z, bus.adr))]),
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((dummy + wbone_width//spi_width)*div,
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[dq_oe.eq(0)]),
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(1,
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[bus.ack.eq(1), cs_n.eq(1)]),
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(div, # tSHSL!
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[bus.ack.eq(0)]),
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(0,
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[]),
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]
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# accumulate timeline deltas
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t, tseq = 0, []
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for dt, a in seq:
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tseq.append((t, a))
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t += dt
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self.sync += timeline(bus.cyc & bus.stb & (i == div - 1), tseq)
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