26 lines
771 B
Python
26 lines
771 B
Python
from migen.fhdl.structure import *
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from migen.fhdl import verilog
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from migen.bank import description, csrgen
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ninputs = 4
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noutputs = 4
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oreg = description.Register("o")
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ofield = description.Field(oreg, "val", noutputs)
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ireg = description.Register("i")
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ifield = description.Field(ireg, "val", ninputs, description.READ_ONLY, description.WRITE_ONLY)
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# input path
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gpio_in = Signal(BV(ninputs))
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gpio_in_s = Signal(BV(ninputs)) # synchronizer
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incomb = [ifield.dev_we.eq(1)]
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insync = [gpio_in_s.eq(gpio_in), ifield.dev_w.eq(gpio_in_s)]
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inf = Fragment(incomb, insync)
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bank = csrgen.Bank([oreg, ireg])
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f = bank.get_fragment() + inf
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i = bank.interface
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ofield.dev_r.name_override = "gpio_out"
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v = verilog.convert(f, {i.d_o, ofield.dev_r, i.a_i, i.we_i, i.d_i, gpio_in})
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print(v)
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