170 lines
2.7 KiB
Verilog
170 lines
2.7 KiB
Verilog
`timescale 1ns / 1ps
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module tb_s6ddrphy();
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reg sys_clk = 1'b0;
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reg clk2x_270 = 1'b0;
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reg clk4x_wr = 1'b0;
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wire clk4x_wr_strb;
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wire clk4x_rd = clk4x_wr;
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wire clk4x_rd_strb = clk4x_wr_strb;
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initial begin
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while(1) begin
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sys_clk <= 1'b1;
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#6;
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sys_clk <= 1'b0;
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#6;
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end
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end
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initial begin
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#4.5;
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while(1) begin
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clk2x_270 <= 1'b1;
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#3;
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clk2x_270 <= 1'b0;
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#3;
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end
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end
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initial begin
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while(1) begin
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clk4x_wr <= 1'b1;
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#1.5;
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clk4x_wr <= 1'b0;
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#1.5;
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end
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end
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BUFPLL #(
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.DIVIDE(4)
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) bufpll (
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.PLLIN(clk4x_wr),
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.GCLK(sys_clk),
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.LOCKED(1'b1),
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.IOCLK(),
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.LOCK(),
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.SERDESSTROBE(clk4x_wr_strb)
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);
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reg [12:0] dfi_address_p0 = 0;
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reg [12:0] dfi_address_p1 = 0;
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reg dfi_wrdata_en_p0 = 0;
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reg [7:0] dfi_wrdata_mask_p0 = 0;
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reg [63:0] dfi_wrdata_p0 = 0;
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reg dfi_wrdata_en_p1 = 0;
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reg [7:0] dfi_wrdata_mask_p1 = 0;
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reg [63:0] dfi_wrdata_p1 = 0;
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reg dfi_rddata_en_p0 = 0;
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reg dfi_rddata_en_p1 = 0;
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wire [31:0] sd_dq;
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reg [31:0] dq_tb = 32'hzzzzzzzz;
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assign sd_dq = dq_tb;
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s6ddrphy #(
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.NUM_AD(13),
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.NUM_BA(2),
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.NUM_D(64)
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) dut (
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.sys_clk(sys_clk),
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.clk2x_270(clk2x_270),
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.clk4x_wr(clk4x_wr),
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.clk4x_wr_strb(clk4x_wr_strb),
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.clk4x_rd(clk4x_rd),
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.clk4x_rd_strb(clk4x_rd_strb),
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.sd_clk_out_p(),
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.sd_clk_out_n(),
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.dfi_address_p0(dfi_address_p0),
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.dfi_address_p1(dfi_address_p1),
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.sd_a(),
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.dfi_wrdata_en_p0(dfi_wrdata_en_p0),
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.dfi_wrdata_mask_p0(dfi_wrdata_mask_p0),
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.dfi_wrdata_p0(dfi_wrdata_p0),
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.dfi_wrdata_en_p1(dfi_wrdata_en_p1),
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.dfi_wrdata_mask_p1(dfi_wrdata_mask_p1),
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.dfi_wrdata_p1(dfi_wrdata_p1),
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.sd_dq(sd_dq),
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.sd_dm(),
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.sd_dqs(),
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.dfi_rddata_en_p0(dfi_rddata_en_p0),
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.dfi_rddata_en_p1(dfi_rddata_en_p1),
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.dfi_rddata_w0(),
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.dfi_rddata_w1(),
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.dfi_rddata_valid_w0(),
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.dfi_rddata_valid_w1()
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);
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`define TEST_SIMPLE_CMD
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`define TEST_WRITE
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`define TEST_READ
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initial begin
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$dumpfile("s6ddrphy.vcd");
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$dumpvars(3, dut);
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`ifdef TEST_SIMPLE_CMD
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#13;
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dfi_address_p0 <= 13'h1aba;
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dfi_address_p1 <= 13'h1234;
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#12;
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dfi_address_p0 <= 0;
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dfi_address_p1 <= 0;
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#59;
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`endif
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`ifdef TEST_WRITE
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#13;
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dfi_address_p1 <= 13'h0dbe;
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dfi_wrdata_en_p1 <= 1;
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dfi_wrdata_mask_p0 <= 8'h12;
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dfi_wrdata_mask_p1 <= 8'h34;
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dfi_wrdata_p0 <= 64'hcafebabeabadface;
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dfi_wrdata_p1 <= 64'h0123456789abcdef;
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#12;
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dfi_address_p1 <= 0;
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dfi_wrdata_en_p1 <= 0;
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dfi_wrdata_mask_p0 <= 0;
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dfi_wrdata_mask_p1 <= 0;
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dfi_wrdata_p0 <= 64'd0;
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dfi_wrdata_p1 <= 64'd0;
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#59;
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`endif
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`ifdef TEST_READ
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#13;
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dfi_address_p0 <= 13'h1234;
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dfi_rddata_en_p0 <= 1;
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#12;
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dfi_address_p0 <= 0;
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dfi_rddata_en_p0 <= 0;
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#15.5;
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dq_tb <= 32'h12345678;
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#3;
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dq_tb <= 32'hdeadbeef;
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#3;
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dq_tb <= 32'hcafebabe;
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#3;
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dq_tb <= 32'habadface;
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#3;
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dq_tb <= 32'hzzzzzzzz;
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#60;
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`endif
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$finish;
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end
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endmodule
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module glbl();
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wire GSR = 1'b0;
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wire GTS = 1'b0;
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endmodule
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