143 lines
3.2 KiB
Python
143 lines
3.2 KiB
Python
from migen.fhdl.std import *
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from migen.genlib.fsm import FSM, NextState
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from lib.sata.std import *
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from lib.sata.link.crc import SATACRCInserter, SATACRCChecker
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from lib.sata.link.scrambler import SATAScrambler
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# Todo:
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# - TX: (optional) insert COND and scramble between COND and primitives
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# - RX: manage COND, HOLD from device
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class SATALinkLayer(Module):
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def __init__(self, phy):
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self.sink = Sink(link_layout(32))
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self.source = Source(link_layout(32))
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fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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# TX
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# insert CRC
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crc_inserter = SATACRCInserter(link_layout(32))
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self.submodules += crc_inserter
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# scramble
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scrambler = SATAScrambler(link_layout(32))
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self.submodules += scrambler
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# graph
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self.comb += [
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Record.connect(self.sink, crc_inserter.sink),
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Record.connect(crc_inserter.source, scrambler.sink)
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]
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# datas / primitives mux
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tx_insert = Signal(32)
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self.comb += [
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If(tx_insert != 0,
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phy.sink.stb.eq(1),
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phy.sink.data.eq(tx_insert),
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phy.sink.charisk.eq(0x0001),
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).Elif(fsm.ongoing("H2D_COPY"),
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phy.sink.stb.eq(scrambler.source.stb),
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phy.sink.data.eq(scrambler.source.d),
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scrambler.source.ack.eq(phy.source.ack),
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phy.sink.charisk.eq(0)
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)
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]
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# RX
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# datas / primitives detection
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rx_det = Signal(32)
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self.comb += \
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If(phy.source.stb & (phy.source.charisk == 0b0001),
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rx_det.eq(phy.source.data)
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)
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# descrambler
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descrambler = SATAScrambler(link_layout(32))
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self.submodules += descrambler
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# check CRC
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crc_checker = SATACRCChecker(link_layout(32))
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self.submodules += crc_checker
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# graph
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self.comb += [
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If(fsm.ongoing("H2D_COPY") & (rx_det == 0),
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descrambler.sink.stb.eq(phy.source.stb & (phy.source.charisk == 0)),
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descrambler.sink.d.eq(phy.source.data),
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),
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phy.source.ack.eq(1),
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Record.connect(descrambler.source, crc_checker.sink),
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Record.connect(crc_checker.source, self.source)
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]
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# FSM
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fsm.act("IDLE",
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tx_insert.eq(primitives["SYNC"]),
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If(rx_det == primitives["X_RDY"],
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NextState("D2H_RDY")
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).Elif(scrambler.source.stb & scrambler.source.sop,
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NextState("H2D_RDY")
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)
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)
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# Host to Device
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fsm.act("H2D_RDY",
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tx_insert.eq(primitives["X_RDY"]),
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If(rx_det == primitives["R_RDY"],
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NextState("H2D_SOF")
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)
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)
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fsm.act("H2D_SOF",
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tx_insert.eq(primitives["SOF"]),
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If(phy.sink.ack,
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NextState("H2D_COPY")
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)
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)
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fsm.act("H2D_COPY",
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If(scrambler.source.stb & scrambler.source.eop & scrambler.source.ack,
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NextState("H2D_EOF")
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)
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)
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fsm.act("H2D_EOF",
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tx_insert.eq(primitives["EOF"]),
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If(phy.sink.ack,
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NextState("H2D_WTRM")
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)
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)
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fsm.act("H2D_WTRM",
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tx_insert.eq(primitives["WTRM"]),
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If(rx_det == primitives["R_OK"],
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NextState("IDLE")
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).Elif(rx_det == primitives["R_ERR"],
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NextState("IDLE")
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)
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)
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# Device to Host
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fsm.act("D2H_RDY",
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tx_insert.eq(primitives["R_RDY"]),
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If(rx_det == primitives["SOF"],
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NextState("D2H_COPY")
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)
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)
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fsm.act("D2H_COPY",
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If(rx_det == primitives["EOF"],
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NextState("D2H_WTRM")
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)
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)
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fsm.act("D2H_EOF",
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If(rx_det == primitives["WTRM"],
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NextState("D2H_WTRM")
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)
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)
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fsm.act("D2H_WTRM",
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tx_insert.eq(primitives["R_OK"]),
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If(rx_det == primitives["SYNC"],
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NextState("IDLE")
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)
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)
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