94 lines
2.2 KiB
Python
94 lines
2.2 KiB
Python
from migen.fhdl.std import *
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from migen.genlib.misc import optree
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from lib.sata.std import *
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@DecorateModule(InsertReset)
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@DecorateModule(InsertCE)
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class Scrambler(Module):
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"""SATA Scrambler
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Implement a SATA Scrambler
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Attributes
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----------
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value : out
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Scrambled value.
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"""
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def __init__(self):
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self.value = Signal(32)
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###
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context = Signal(16, reset=0xf0f6)
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next_value = Signal(32)
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self.sync += context.eq(next_value[16:32])
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# from SATA specification, if possible replace it
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# with a generic implementation using polynoms.
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lfsr_coefs = (
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(15, 13, 4, 0), #0
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(15, 14, 13, 5, 4, 1, 0),
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(14, 13, 6, 5, 4, 2,1, 0),
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(15, 14, 7, 6, 5, 3,2, 1),
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(13, 8, 7, 6, 3, 2, 0),
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(14, 9, 8, 7, 4, 3, 1),
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(15, 10, 9, 8, 5, 4, 2),
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(15, 13, 11, 10, 9, 6, 5, 4, 3, 0),
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(15, 14, 13, 12, 11, 10,7, 6, 5, 1, 0),
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(14, 12, 11, 8, 7, 6, 4, 2, 1, 0),
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(15, 13, 12, 9, 8, 7, 5, 3, 2, 1),
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(15, 14, 10, 9, 8, 6, 3, 2, 0),
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(13, 11, 10, 9, 7, 3, 1, 0),
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(14, 12, 11, 10, 8, 4, 2, 1),
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(15, 13, 12, 11, 9, 5, 3, 2),
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(15, 14, 12, 10, 6, 3, 0),
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(11, 7, 1, 0), #16
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(12, 8, 2, 1),
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(13, 9, 3, 2),
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(14, 10, 4, 3),
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(15, 11, 5, 4),
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(15, 13, 12, 6, 5, 4, 0),
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(15, 14, 7, 6, 5, 4, 1, 0),
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(13, 8, 7, 6, 5, 4, 2, 1, 0),
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(14, 9, 8,7, 6, 5, 3, 2, 1),
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(15, 10, 9, 8, 7, 6, 4, 3, 2),
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(15, 13, 11, 10, 9, 8, 7, 5, 3, 0),
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(15, 14, 13, 12, 11, 10, 9, 8, 6, 1, 0),
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(14, 12, 11, 10, 9, 7, 4, 2, 1, 0),
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(15, 13, 12, 11, 10, 8, 5, 3, 2, 1),
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(15, 14, 12, 11, 9, 6, 3, 2, 0),
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(12, 10, 7, 3, 1, 0),
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)
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for n, coefs in enumerate(lfsr_coefs):
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eq = [context[i] for i in coefs]
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self.comb += next_value[n].eq(optree("^", eq))
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self.comb += self.value.eq(next_value)
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class SATAScrambler(Module):
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def __init__(self, layout):
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self.sink = sink = Sink(layout)
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self.source = source = Source(layout)
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###
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self.submodules.scrambler = Scrambler()
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ongoing = Signal()
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self.sync += \
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If(sink.stb & sink.ack,
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If(sink.eop,
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ongoing.eq(0)
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).Elif(sink.sop,
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ongoing.eq(1)
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)
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)
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self.comb += [
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self.scrambler.ce.eq(sink.stb & sink.ack & (sink.sop | ongoing)),
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self.scrambler.reset.eq(~(sink.sop | ongoing)),
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Record.connect(sink, source),
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source.d.eq(sink.d ^ self.scrambler.value)
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]
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