115 lines
4.7 KiB
Python
115 lines
4.7 KiB
Python
from migen.fhdl.structure import *
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from migen.fhdl.specials import Memory, _MemoryPort, WRITE_FIRST, NO_CHANGE
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from migen.fhdl.decorators import ModuleTransformer
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from migen.util.misc import gcd_multiple
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class FullMemoryWE(ModuleTransformer):
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def __init__(self):
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self.replacments = dict()
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def transform_fragment(self, i, f):
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newspecials = set()
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for orig in f.specials:
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if not isinstance(orig, Memory):
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newspecials.add(orig)
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continue
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global_granularity = gcd_multiple([p.we_granularity if p.we_granularity else orig.width for p in orig.ports])
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if global_granularity == orig.width:
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newspecials.add(orig) # nothing to do
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else:
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newmems = []
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for i in range(orig.width//global_granularity):
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if orig.init is None:
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newinit = None
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else:
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newinit = [(v >> i*global_granularity) & (2**global_granularity - 1) for v in orig.init]
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newmem = Memory(global_granularity, orig.depth, newinit, orig.name_override + "_grain" + str(i))
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newspecials.add(newmem)
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newmems.append(newmem)
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for port in orig.ports:
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port_granularity = port.we_granularity if port.we_granularity else orig.width
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newport = _MemoryPort(
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adr=port.adr,
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dat_r=port.dat_r[i*global_granularity:(i+1)*global_granularity] if port.dat_r is not None else None,
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we=port.we[i*global_granularity//port_granularity] if port.we is not None else None,
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dat_w=port.dat_w[i*global_granularity:(i+1)*global_granularity] if port.dat_w is not None else None,
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async_read=port.async_read,
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re=port.re,
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we_granularity=0,
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mode=port.mode,
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clock_domain=port.clock)
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newmem.ports.append(newport)
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newspecials.add(newport)
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self.replacments[orig] = newmems
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f.specials = newspecials
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class MemoryToArray(ModuleTransformer):
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def __init__(self):
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self.replacements = dict()
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def transform_fragment(self, i, f):
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newspecials = set()
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for mem in f.specials:
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if not isinstance(mem, Memory):
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newspecials.add(mem)
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continue
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storage = Array()
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self.replacements[mem] = storage
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init = []
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if mem.init is not None:
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init = mem.init
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for d in init:
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mem_storage = Signal(mem.width, reset=d)
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storage.append(mem_storage)
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for _ in range(mem.depth-len(init)):
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mem_storage = Signal(mem.width)
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storage.append(mem_storage)
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for port in mem.ports:
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if port.we_granularity:
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raise NotImplementedError
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try:
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sync = f.sync[port.clock.cd]
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except KeyError:
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sync = f.sync[port.clock.cd] = []
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# read
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if port.async_read:
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f.comb.append(port.dat_r.eq(storage[port.adr]))
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else:
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if port.mode == WRITE_FIRST and port.we is not None:
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adr_reg = Signal.like(port.adr)
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rd_stmt = adr_reg.eq(port.adr)
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f.comb.append(port.dat_r.eq(storage[adr_reg]))
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elif port.mode == NO_CHANGE and port.we is not None:
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rd_stmt = If(~port.we, port.dat_r.eq(storage[port.adr]))
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else: # READ_FIRST or port.we is None, simplest case
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rd_stmt = port.dat_r.eq(storage[port.adr])
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if port.re is None:
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sync.append(rd_stmt)
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else:
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sync.append(If(port.re, rd_stmt))
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# write
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if port.we is not None:
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if port.we_granularity:
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n = mem.width//port.we_granularity
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for i in range(n):
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m = i*port.we_granularity
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M = (i+1)*port.we_granularity
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sync.append(If(port.we[i],
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storage[port.adr][m:M].eq(port.dat_w)))
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else:
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sync.append(If(port.we,
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storage[port.adr].eq(port.dat_w)))
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f.specials = newspecials
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