litex/migen
2014-09-08 18:48:54 +08:00
..
actorlib actorlib/spi: remove unneeded import 2014-09-08 18:48:54 +08:00
bank migen/bank/description: add reset parameter to CSRStatus 2014-06-15 23:54:38 +02:00
bus bus/dfi: add CKE and RESET_N 2014-08-09 10:56:08 +08:00
fhdl fhdl.structure: do not permit clock domain names that start with numbers 2014-08-18 11:01:56 +08:00
flow flow/network: replace NetworkX MultiDiGraph with simple implementation 2014-09-07 16:48:46 +08:00
genlib cordic: round() constants if not power of two bitwidth, cleanup, simplify some logic 2014-09-07 16:49:12 +08:00
pytholite
sim sim/icarus: add vpi directory to module search path 2014-09-07 16:49:12 +08:00
test cordic: round() constants if not power of two bitwidth, cleanup, simplify some logic 2014-09-07 16:49:12 +08:00
util
__init__.py