64 lines
1.8 KiB
Python
64 lines
1.8 KiB
Python
from migen.fhdl.std import *
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from migen.bus import wishbone
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from migen.genlib.io import DifferentialInput
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from misoclib.soc import SoC, mem_decoder
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from misoclib.com.liteeth.phy import LiteEthPHY
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from misoclib.com.liteeth.mac import LiteEthMAC
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class _CRG(Module):
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def __init__(self, clk_crg):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_por = ClockDomain(reset_less=True)
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# Power on Reset (vendor agnostic)
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rst_n = Signal()
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self.sync.por += rst_n.eq(1)
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self.comb += [
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self.cd_sys.clk.eq(clk_crg),
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self.cd_por.clk.eq(clk_crg),
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self.cd_sys.rst.eq(~rst_n)
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]
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class BaseSoC(SoC):
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def __init__(self, platform, **kwargs):
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SoC.__init__(self, platform,
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clk_freq=int((1/(platform.default_clk_period))*1000000000),
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with_rom=True,
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with_sdram=True, sdram_size=16*1024,
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**kwargs)
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clk_in = platform.request(platform.default_clk_name)
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clk_crg = Signal()
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if hasattr(clk_in, "p"):
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self.specials += DifferentialInput(clk_in.p, clk_in.n, clk_crg)
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else:
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self.comb += clk_crg.eq(clk_in)
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self.submodules.crg = _CRG(clk_crg)
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class MiniSoC(BaseSoC):
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csr_map = {
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"ethphy": 20,
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"ethmac": 21
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}
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csr_map.update(BaseSoC.csr_map)
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interrupt_map = {
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"ethmac": 2,
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}
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interrupt_map.update(BaseSoC.interrupt_map)
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mem_map = {
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"ethmac": 0x30000000, # (shadow @0xb0000000)
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}
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mem_map.update(BaseSoC.mem_map)
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def __init__(self, platform, **kwargs):
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BaseSoC.__init__(self, platform, **kwargs)
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self.submodules.ethphy = LiteEthPHY(platform.request("eth_clocks"), platform.request("eth"))
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self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", with_hw_preamble_crc=False)
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self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
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self.add_memory_region("ethmac", self.mem_map["ethmac"]+0x80000000, 0x2000)
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default_subtarget = BaseSoC
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