28 lines
803 B
Python
28 lines
803 B
Python
from migen.fhdl.structure import *
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from migen.bus import wishbone
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class SRAM:
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def __init__(self, depth):
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self.bus = wishbone.Slave()
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self.depth = depth
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def get_fragment(self):
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# generate write enable signal
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we = Signal(BV(4))
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comb = [we[i].eq(self.bus.cyc_i & self.bus.stb_i & self.bus.we_i & self.bus.sel_i[3-i])
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for i in range(4)]
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# split address
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nbits = bits_for(self.depth-1)
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partial_adr = Signal(BV(nbits))
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comb.append(partial_adr.eq(self.bus.adr_i[:nbits]))
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# generate ack
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sync = [
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self.bus.ack_o.eq(0),
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If(self.bus.cyc_i & self.bus.stb_i & ~self.bus.ack_o,
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self.bus.ack_o.eq(1)
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)
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]
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# memory
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port = MemoryPort(partial_adr, self.bus.dat_o, we, self.bus.dat_i, we_granularity=8)
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return Fragment(comb, sync, memories=[Memory(32, self.depth, port)])
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