63 lines
1.6 KiB
Python
63 lines
1.6 KiB
Python
from migen.fhdl.structure import *
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from migen.bank.description import *
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from migen.bank.eventmanager import *
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from migen.bank import csrgen
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class UART:
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def __init__(self, address, clk_freq, baud=115200):
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self._rxtx = RegisterRaw("rxtx", 8)
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self._divisor = RegisterField("divisor", 16, reset=int(clk_freq/baud/16))
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self._tx_event = EventSourceLevel()
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self.events = EventManager(self._tx_event)
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self.bank = csrgen.Bank([self._rxtx, self._divisor] + self.events.get_registers(),
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address=address)
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self.tx = Signal(reset=1)
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self.rx = Signal()
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def get_fragment(self):
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enable16 = Signal()
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enable16_counter = Signal(BV(16))
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comb = [
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enable16.eq(enable16_counter == Constant(0, BV(16)))
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]
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sync = [
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enable16_counter.eq(enable16_counter - 1),
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If(enable16,
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enable16_counter.eq(self._divisor.field.r - 1))
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]
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tx_reg = Signal(BV(8))
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tx_bitcount = Signal(BV(4))
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tx_count16 = Signal(BV(4))
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tx_busy = Signal()
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sync += [
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If(self._rxtx.re,
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tx_reg.eq(self._rxtx.r),
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tx_bitcount.eq(0),
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tx_count16.eq(1),
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tx_busy.eq(1),
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self.tx.eq(0)
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).Elif(enable16 & tx_busy,
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tx_count16.eq(tx_count16 + 1),
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If(tx_count16 == Constant(0, BV(4)),
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tx_bitcount.eq(tx_bitcount + 1),
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If(tx_bitcount == 8,
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self.tx.eq(1)
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).Elif(tx_bitcount == 9,
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self.tx.eq(1),
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tx_busy.eq(0)
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).Else(
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self.tx.eq(tx_reg[0]),
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tx_reg.eq(Cat(tx_reg[1:], 0))
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)
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)
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)
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]
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comb.append(self._tx_event.trigger.eq(tx_busy))
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return self.bank.get_fragment() \
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+ self.events.get_fragment() \
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+ Fragment(comb, sync, pads={self.tx, self.rx})
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