litex/litex/soc
2019-04-12 17:15:09 +02:00
..
cores vexriscv: allow user to use an external variant 2019-03-15 18:16:25 +01:00
integration integration/soc_zynq: fix missing SoCCore.do_finalize 2019-04-01 14:44:37 +02:00
interconnect interconnect/axi: add missing axi signals 2019-04-01 10:23:25 +02:00
software software/libnet/microudp: cleanup eth_init 2019-04-12 17:15:09 +02:00
tools soc/tools/remote/comm_uart: be sure to flush in waiting bytes before read and write 2019-02-16 00:08:24 +01:00
__init__.py litex: reorganize things, first work working version 2015-11-07 17:48:55 +01:00
MISOC_LICENSE litex: reorganize things, first work working version 2015-11-07 17:48:55 +01:00