154 lines
2.8 KiB
Python
154 lines
2.8 KiB
Python
from migen.fhdl.std import *
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from migen.bank.description import *
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from migen.genlib.fsm import FSM, NextState
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class SPIMaster(Module, AutoCSR):
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def __init__(self, pads, width=24, div=2, cpha=1):
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self.pads = pads
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self._ctrl = CSR()
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self._length = CSRStorage(8)
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self._status = CSRStatus()
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if hasattr(pads, "mosi"):
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self._mosi = CSRStorage(width)
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if hasattr(pads, "miso"):
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self._miso = CSRStatus(width)
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self.irq = Signal()
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###
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# ctrl
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start = Signal()
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length = self._length.storage
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enable_cs = Signal()
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enable_shift = Signal()
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done = Signal()
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self.comb += [
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start.eq(self._ctrl.re & self._ctrl.r[0]),
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self._status.status.eq(done)
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]
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# clk
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i = Signal(max=div)
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clk_en = Signal()
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set_clk = Signal()
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clr_clk = Signal()
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self.sync += [
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If(set_clk,
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pads.clk.eq(enable_cs)
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),
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If(clr_clk,
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pads.clk.eq(0),
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i.eq(0)
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).Else(
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i.eq(i + 1),
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)
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]
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self.comb +=[
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set_clk.eq(i==div//2-1),
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clr_clk.eq(i==div-1)
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]
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# fsm
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cnt = Signal(8)
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clr_cnt = Signal()
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inc_cnt = Signal()
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self.sync += \
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If(clr_cnt,
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cnt.eq(0)
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).Elif(inc_cnt,
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cnt.eq(cnt+1)
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)
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fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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fsm.act("IDLE",
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If(start,
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NextState("WAIT_CLK")
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),
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done.eq(1),
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clr_cnt.eq(1)
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)
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fsm.act("WAIT_CLK",
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If(clr_clk,
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NextState("SHIFT")
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),
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)
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fsm.act("SHIFT",
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If(cnt == length,
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NextState("END")
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).Else(
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inc_cnt.eq(clr_clk),
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),
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enable_cs.eq(1),
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enable_shift.eq(1),
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)
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fsm.act("END",
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If(set_clk,
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NextState("IDLE")
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),
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enable_shift.eq(1),
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self.irq.eq(1)
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)
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# miso
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if hasattr(pads, "miso"):
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miso = Signal()
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sr_miso = Signal(width)
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# (cpha = 1: capture on clk falling edge)
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if cpha:
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self.sync += \
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If(enable_shift,
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If(clr_clk,
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miso.eq(pads.miso),
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).Elif(set_clk,
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sr_miso.eq(Cat(miso, sr_miso[:-1]))
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)
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)
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# (cpha = 0: capture on clk rising edge)
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else:
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self.sync += \
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If(enable_shift,
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If(set_clk,
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miso.eq(pads.miso),
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).Elif(clr_clk,
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sr_miso.eq(Cat(miso, sr_miso[:-1]))
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)
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)
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self.comb += self._miso.status.eq(sr_miso)
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# mosi
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if hasattr(pads, "mosi"):
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mosi = Signal()
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sr_mosi = Signal(width)
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# (cpha = 1: propagated on clk rising edge)
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if cpha:
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self.sync += \
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If(start,
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sr_mosi.eq(self._mosi.storage)
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).Elif(clr_clk & enable_shift,
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sr_mosi.eq(Cat(Signal(), sr_mosi[:-1]))
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).Elif(set_clk,
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pads.mosi.eq(sr_mosi[-1])
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)
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# (cpha = 0: propagated on clk falling edge)
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else:
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self.sync += [
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If(start,
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sr_mosi.eq(self._mosi.storage)
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).Elif(set_clk & enable_shift,
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sr_mosi.eq(Cat(Signal(), sr_mosi[:-1]))
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).Elif(clr_clk,
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pads.mosi.eq(sr_mosi[-1])
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)
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]
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# cs_n
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self.comb += pads.cs_n.eq(~enable_cs)
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