55 lines
1.4 KiB
Python
55 lines
1.4 KiB
Python
#
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# This file is part of LiteX.
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#
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# Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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import unittest
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from migen import *
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from litex.soc.cores.icap import *
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iprog_sequence = [
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# csib rdwrb data
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"0 0 0xaa995566",
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"0 0 0x20000000",
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"0 0 0x20000000",
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"0 0 0x30008001",
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"0 0 0x0000000f",
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"0 0 0x20000000",
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"0 0 0x20000000",
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"0 0 0x30008001",
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"0 0 0x0000000d",
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"0 0 0x20000000",
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"0 0 0x20000000",
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]
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class TestICAP(unittest.TestCase):
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def test_icap_command_reload(self):
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def generator(dut):
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yield dut.addr.eq(ICAPRegisters.CMD)
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yield dut.data.eq(ICAPCMDs.IPROG)
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for i in range(8):
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yield
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yield dut.send.eq(1)
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yield
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yield dut.send.eq(0)
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def check(dut):
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while (yield dut._i) != ICAP_SYNC:
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yield
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for ref_w in iprog_sequence:
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cur_w = f"{(yield dut._csib)} {(yield dut._rdwrb)} 0x{(yield dut._i):08x}"
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self.assertEqual(ref_w, cur_w)
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#print(cur_w)
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yield
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dut = ICAP(with_csr=False, simulation=True)
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clocks = {"sys": 10, "icap": 10}
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run_simulation(dut, [generator(dut), check(dut)], clocks, vcd_name="icap.vcd")
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def test_icap_bitstream_syntax(self):
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dut = ICAPBitstream(simulation=True)
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