28 lines
1.8 KiB
HTML
28 lines
1.8 KiB
HTML
<img alt="./_static/LiteScope_logo_full.png" src="_static/LiteScope_logo_full.png">
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<h3>A small footprint and configurable embedded FPGA logic analyzer core</b>.</h3>
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<div class="container" style="width:100%;margin-bottom:10px;">
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<div class="one-third-container" style="width:32%; display:inline-block;">
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<div class="signpost" style="display:inline-block; vertical-align:text-top; margin-left:5px;margin-right:5px;">
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<div class="signpost-heading" style="font-size:2em; font-style:bold; margin-bottom:10px;">Small footprint</div>
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<div class="signpost-body" style=""><p>Thanks to simple and efficient Migen's building blocks and the KISS principe used to develop this core, LiteScope footprint is really small!</p></div>
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</div>
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</div>
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<div class="one-third-container" style="width:32%; display:inline-block; font-style:bold;">
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<div class="signpost" style="display:inline-block; vertical-align:text-top; margin-left:5px;margin-right:5px;">
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<div class="signpost-heading" style="font-size:2em; font-style:bold; margin-bottom:10px;">Configurable</div>
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<div class="signpost-body" style=""><p>LiteScope generates HDL using Migen as a Python meta-language. The core is then easily configurable to fit user's needs! (Data width, storage depth, storage qualifier and so on...)</p></div>
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</div>
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</div>
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<div class="one-third-container" style="width:32%; display:inline-block; font-style:bold;">
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<div class="signpost" style="display:inline-block; vertical-align:text-top; margin-left:5px; margin-right:5px;">
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<div class="signpost-heading" style="font-size:2em; font-style:bold; margin-bottom:10px;">Portable</div>
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<div class="signpost-body" style=""><p>Liscope can target all FPGAs regardless of the vendor, so you keep
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your debug methology accross all the FPGA designs you are developing!</p></div>
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</div>
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</div>
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</div>
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