78 lines
2.2 KiB
Python
78 lines
2.2 KiB
Python
from migen.genlib.io import DDROutput
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from misoclib.com.liteeth.common import *
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from misoclib.com.liteeth.generic import *
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class LiteEthPHYGMIITX(Module):
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def __init__(self, pads, pads_register):
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self.sink = sink = Sink(eth_phy_description(8))
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###
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if hasattr(pads, "tx_er"):
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self.sync += pads.tx_er.eq(0)
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pads_eq = [
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pads.tx_en.eq(sink.stb),
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pads.tx_data.eq(sink.data)
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]
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if pads_register:
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self.sync += pads_eq
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else:
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self.comb += pads_eq
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self.comb += sink.ack.eq(1)
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class LiteEthPHYGMIIRX(Module):
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def __init__(self, pads):
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self.source = source = Source(eth_phy_description(8))
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###
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dv_d = Signal()
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self.sync += dv_d.eq(pads.dv)
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sop = Signal()
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eop = Signal()
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self.comb += [
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sop.eq(pads.dv & ~dv_d),
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eop.eq(~pads.dv & dv_d)
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]
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self.sync += [
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source.stb.eq(pads.dv),
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source.sop.eq(sop),
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source.data.eq(pads.rx_data)
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]
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self.comb += source.eop.eq(eop)
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class LiteEthPHYGMIICRG(Module, AutoCSR):
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def __init__(self, clock_pads, pads, with_hw_init_reset):
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self._reset = CSRStorage()
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###
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self.clock_domains.cd_eth_rx = ClockDomain()
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self.clock_domains.cd_eth_tx = ClockDomain()
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self.specials += DDROutput(1, 0, clock_pads.gtx, ClockSignal("eth_tx"))
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self.comb += [
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self.cd_eth_rx.clk.eq(clock_pads.rx), # Let the synthesis tool insert
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self.cd_eth_tx.clk.eq(self.cd_eth_rx.clk) # the appropriate clock buffer
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]
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if with_hw_init_reset:
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reset = Signal()
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counter_done = Signal()
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self.submodules.counter = counter = Counter(max=512)
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self.comb += [
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counter_done.eq(counter.value == 256),
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counter.ce.eq(~counter_done),
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reset.eq(~counter_done | self._reset.storage)
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]
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else:
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reset = self._reset.storage
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self.comb += pads.rst_n.eq(~reset)
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self.specials += [
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AsyncResetSynchronizer(self.cd_eth_tx, reset),
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AsyncResetSynchronizer(self.cd_eth_rx, reset),
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]
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class LiteEthPHYGMII(Module, AutoCSR):
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def __init__(self, clock_pads, pads, with_hw_init_reset=True):
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self.dw = 8
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self.submodules.crg = LiteEthPHYGMIICRG(clock_pads, pads, with_hw_init_reset)
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self.submodules.tx = RenameClockDomains(LiteEthPHYGMIITX(pads), "eth_tx")
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self.submodules.rx = RenameClockDomains(LiteEthPHYGMIIRX(pads), "eth_rx")
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self.sink, self.source = self.tx.sink, self.rx.source
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