185 lines
6.2 KiB
Python
185 lines
6.2 KiB
Python
# Simple Processor Interface
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from migen.fhdl.std import *
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from migen.bank.description import *
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from migen.flow.actor import *
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from migen.flow.network import *
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from migen.flow import plumbing
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from migen.actorlib import misc
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# layout is a list of tuples, either:
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# - (name, nbits, [reset value], [alignment bits])
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# - (name, sublayout)
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def _convert_layout(layout):
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r = []
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for element in layout:
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if isinstance(element[1], list):
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r.append((element[0], _convert_layout(element[1])))
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else:
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r.append((element[0], element[1]))
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return r
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(MODE_EXTERNAL, MODE_SINGLE_SHOT, MODE_CONTINUOUS) = range(3)
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class SingleGenerator(Module, AutoCSR):
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def __init__(self, layout, mode):
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self.source = Source(_convert_layout(layout))
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self.busy = Signal()
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self.comb += self.busy.eq(self.source.stb)
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if mode == MODE_EXTERNAL:
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self.trigger = Signal()
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trigger = self.trigger
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elif mode == MODE_SINGLE_SHOT:
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self._shoot = CSR()
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trigger = self._shoot.re
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elif mode == MODE_CONTINUOUS:
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self._enable = CSRStorage()
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trigger = self._enable.storage
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else:
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raise ValueError
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self.sync += If(self.source.ack | ~self.source.stb, self.source.stb.eq(trigger))
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self._create_csrs(layout, self.source.payload, mode != MODE_SINGLE_SHOT)
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def _create_csrs(self, layout, target, atomic, prefix=""):
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for element in layout:
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if isinstance(element[1], list):
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self._create_csrs(element[1], atomic,
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getattr(target, element[0]),
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element[0] + "_")
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else:
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name = element[0]
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nbits = element[1]
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if len(element) > 2:
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reset = element[2]
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else:
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reset = 0
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if len(element) > 3:
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alignment = element[3]
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else:
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alignment = 0
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regname = prefix + name
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reg = CSRStorage(nbits + alignment, reset=reset, atomic_write=atomic,
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alignment_bits=alignment, name=regname)
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setattr(self, "r_"+regname, reg)
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self.sync += If(self.source.ack | ~self.source.stb,
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getattr(target, name).eq(reg.storage))
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class Collector(Module, AutoCSR):
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def __init__(self, layout, depth=1024):
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self.sink = Sink(layout)
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self.busy = Signal()
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dw = sum(len(s) for s in self.sink.payload.flatten())
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self._wa = CSRStorage(bits_for(depth-1), write_from_dev=True)
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self._wc = CSRStorage(bits_for(depth), write_from_dev=True, atomic_write=True)
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self._ra = CSRStorage(bits_for(depth-1))
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self._rd = CSRStatus(dw)
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###
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mem = Memory(dw, depth)
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self.specials += mem
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wp = mem.get_port(write_capable=True)
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rp = mem.get_port()
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self.specials += wp, rp
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self.comb += [
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self.busy.eq(0),
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If(self._wc.r != 0,
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self.sink.ack.eq(1),
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If(self.sink.stb,
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self._wa.we.eq(1),
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self._wc.we.eq(1),
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wp.we.eq(1)
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)
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),
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self._wa.dat_w.eq(self._wa.storage + 1),
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self._wc.dat_w.eq(self._wc.storage - 1),
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wp.adr.eq(self._wa.storage),
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wp.dat_w.eq(self.sink.payload.raw_bits()),
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rp.adr.eq(self._ra.storage),
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self._rd.status.eq(rp.dat_r)
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]
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class _DMAController(Module):
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def __init__(self, bus_accessor, bus_aw, bus_dw, mode, base_reset=0, length_reset=0):
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self.alignment_bits = bits_for(bus_dw//8) - 1
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layout = [
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("length", bus_aw + self.alignment_bits, length_reset, self.alignment_bits),
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("base", bus_aw + self.alignment_bits, base_reset, self.alignment_bits)
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]
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self.generator = SingleGenerator(layout, mode)
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self.r_busy = CSRStatus()
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self.length = self.generator.r_length.storage
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self.base = self.generator.r_base.storage
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if hasattr(self.generator, "trigger"):
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self.trigger = self.generator.trigger
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def get_csrs(self):
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return self.generator.get_csrs() + [self.r_busy]
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class DMAReadController(_DMAController):
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def __init__(self, bus_accessor, *args, **kwargs):
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bus_aw = flen(bus_accessor.address.a)
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bus_dw = flen(bus_accessor.data.d)
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_DMAController.__init__(self, bus_accessor, bus_aw, bus_dw, *args, **kwargs)
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g = DataFlowGraph()
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g.add_pipeline(self.generator,
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misc.IntSequence(bus_aw, bus_aw),
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AbstractActor(plumbing.Buffer),
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bus_accessor,
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AbstractActor(plumbing.Buffer))
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comp_actor = CompositeActor(g)
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self.submodules += comp_actor
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self.data = comp_actor.q
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self.busy = comp_actor.busy
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self.comb += self.r_busy.status.eq(self.busy)
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class DMAWriteController(_DMAController):
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def __init__(self, bus_accessor, *args, ack_when_inactive=False, **kwargs):
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bus_aw = flen(bus_accessor.address_data.a)
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bus_dw = flen(bus_accessor.address_data.d)
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_DMAController.__init__(self, bus_accessor, bus_aw, bus_dw, *args, **kwargs)
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g = DataFlowGraph()
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adr_buffer = AbstractActor(plumbing.Buffer)
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int_sequence = misc.IntSequence(bus_aw, bus_aw)
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g.add_pipeline(self.generator,
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int_sequence,
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adr_buffer)
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g.add_connection(adr_buffer, bus_accessor, sink_subr=["a"])
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g.add_connection(AbstractActor(plumbing.Buffer), bus_accessor, sink_subr=["d"])
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comp_actor = CompositeActor(g)
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self.submodules += comp_actor
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if ack_when_inactive:
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demultiplexer = plumbing.Demultiplexer([("d", bus_dw)], 2)
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self.comb +=[
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demultiplexer.sel.eq(~adr_buffer.busy),
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demultiplexer.source0.connect(comp_actor.d),
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demultiplexer.source1.ack.eq(1),
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]
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self.submodules += demultiplexer
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self.data = demultiplexer.sink
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else:
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self.data = comp_actor.d
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self.busy = comp_actor.busy
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self.comb += self.r_busy.status.eq(self.busy)
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