31 lines
831 B
Python
31 lines
831 B
Python
from migen.fhdl.std import *
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from migen.fhdl import verilog
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from migen.genlib.fsm import FSM, NextState, NextValue
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class Example(Module):
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def __init__(self):
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self.s = Signal()
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self.counter = Signal(8)
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myfsm = FSM()
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self.submodules += myfsm
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myfsm.act("FOO",
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self.s.eq(1),
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NextState("BAR")
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)
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myfsm.act("BAR",
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self.s.eq(0),
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NextValue(self.counter, self.counter + 1),
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NextState("FOO")
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)
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self.be = myfsm.before_entering("FOO")
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self.ae = myfsm.after_entering("FOO")
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self.bl = myfsm.before_leaving("FOO")
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self.al = myfsm.after_leaving("FOO")
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example = Example()
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print(verilog.convert(example, {example.s, example.counter, example.be, example.ae, example.bl, example.al}))
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