85 lines
3.7 KiB
Python
85 lines
3.7 KiB
Python
from migen.fhdl.std import *
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from migen.bus import wishbone
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from migen.genlib.record import *
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from misoclib.mem.sdram.core import SDRAMCore
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from misoclib.mem.sdram.core.lasmicon import LASMIconSettings
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from misoclib.mem.sdram.core.minicon import MiniconSettings
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from misoclib.mem.sdram.frontend import memtest, wishbone2lasmi
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from misoclib.soc import SoC
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class SDRAMSoC(SoC):
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csr_map = {
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"sdram": 8,
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"wishbone2lasmi": 9,
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"memtest_w": 10,
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"memtest_r": 11
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}
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csr_map.update(SoC.csr_map)
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def __init__(self, platform, clk_freq, sdram_controller_settings,
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**kwargs):
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SoC.__init__(self, platform, clk_freq, **kwargs)
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if isinstance(sdram_controller_settings, str):
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self.sdram_controller_settings = eval(sdram_controller_settings)
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else:
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self.sdram_controller_settings = sdram_controller_settings
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self._sdram_phy_registered = False
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def register_sdram_phy(self, phy):
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if self._sdram_phy_registered:
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raise FinalizeError
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self._sdram_phy_registered = True
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if isinstance(self.sdram_controller_settings, MiniconSettings) and phy.settings.memtype != "SDR":
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raise NotImplementedError("Minicon only supports SDR memtype for now (" + phy.settings.memtype + ")")
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# Core
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self.submodules.sdram = SDRAMCore(phy, phy.module.geom_settings, phy.module.timing_settings, self.sdram_controller_settings)
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dfi_databits_divisor = 1 if phy.settings.memtype == "SDR" else 2
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sdram_width = phy.settings.dfi_databits//dfi_databits_divisor
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main_ram_size = 2**(phy.module.geom_settings.bankbits+
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phy.module.geom_settings.rowbits+
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phy.module.geom_settings.colbits)*sdram_width//8
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# XXX: Limit main_ram_size to 256MB, we should modify mem_map to allow larger memories.
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main_ram_size = min(main_ram_size, 256*1024*1024)
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# LASMICON frontend
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if isinstance(self.sdram_controller_settings, LASMIconSettings):
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if self.sdram_controller_settings.with_bandwidth:
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self.sdram.controller.multiplexer.add_bandwidth()
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if self.sdram_controller_settings.with_memtest:
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self.submodules.memtest_w = memtest.MemtestWriter(self.sdram.crossbar.get_master())
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self.submodules.memtest_r = memtest.MemtestReader(self.sdram.crossbar.get_master())
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l2_size = self.sdram_controller_settings.l2_size
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if l2_size:
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# XXX Vivado 2014.X workaround, Vivado is not able to map correctly our L2 cache.
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# Issue is reported to Xilinx and should be fixed in next releases (2015.1?).
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# Remove this workaround when fixed by Xilinx.
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from mibuild.xilinx.vivado import XilinxVivadoToolchain
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if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
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from migen.fhdl.simplify import FullMemoryWE
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self.submodules.wishbone2lasmi = FullMemoryWE(wishbone2lasmi.WB2LASMI(l2_size//4, self.sdram.crossbar.get_master()))
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else:
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self.submodules.wishbone2lasmi = wishbone2lasmi.WB2LASMI(l2_size//4, self.sdram.crossbar.get_master())
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self.register_mem("main_ram", self.mem_map["main_ram"], self.wishbone2lasmi.wishbone, main_ram_size)
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# MINICON frontend
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elif isinstance(self.sdram_controller_settings, MiniconSettings):
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if sdram_width == 32:
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self.register_mem("main_ram", self.mem_map["main_ram"], self.sdram.controller.bus, main_ram_size)
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elif sdram_width < 32:
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self.submodules.downconverter = downconverter = wishbone.DownConverter(32, sdram_width)
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self.comb += Record.connect(downconverter.wishbone_o, self.sdram.controller.bus)
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self.register_mem("main_ram", self.mem_map["main_ram"], downconverter.wishbone_i, main_ram_size)
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else:
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raise NotImplementedError("Unsupported SDRAM width of {} > 32".format(sdram_width))
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def do_finalize(self):
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if not self.integrated_main_ram_size:
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if not self._sdram_phy_registered:
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raise FinalizeError("Need to call SDRAMSoC.register_sdram_phy()")
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SoC.do_finalize(self)
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