153 lines
2.9 KiB
Verilog
153 lines
2.9 KiB
Verilog
/* TODO: use behavioral BRAM models (Xst can extract byte WE) */
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module minimac3_memory(
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input sys_clk,
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input sys_rst,
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input phy_rx_clk,
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input phy_tx_clk,
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input [29:0] wb_adr_i,
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output [31:0] wb_dat_o,
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input [31:0] wb_dat_i,
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input [3:0] wb_sel_i,
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input wb_stb_i,
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input wb_cyc_i,
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output reg wb_ack_o,
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input wb_we_i,
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input [7:0] rxb0_dat,
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input [10:0] rxb0_adr,
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input rxb0_we,
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input [7:0] rxb1_dat,
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input [10:0] rxb1_adr,
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input rxb1_we,
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output [7:0] txb_dat,
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input [10:0] txb_adr
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);
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wire wb_en = wb_cyc_i & wb_stb_i;
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wire [1:0] wb_buf = wb_adr_i[10:9];
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wire [31:0] wb_dat_i_le = {wb_dat_i[7:0], wb_dat_i[15:8], wb_dat_i[23:16], wb_dat_i[31:24]};
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wire [3:0] wb_sel_i_le = {wb_sel_i[0], wb_sel_i[1], wb_sel_i[2], wb_sel_i[3]};
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wire [31:0] rxb0_wbdat;
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RAMB16BWER #(
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.DATA_WIDTH_A(36),
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.DATA_WIDTH_B(9),
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.DOA_REG(0),
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.DOB_REG(0),
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.EN_RSTRAM_A("FALSE"),
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.EN_RSTRAM_B("FALSE"),
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.SIM_DEVICE("SPARTAN6"),
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.WRITE_MODE_A("WRITE_FIRST"),
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.WRITE_MODE_B("WRITE_FIRST")
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) rxb0 (
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.DIA(wb_dat_i_le),
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.DIPA(4'd0),
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.DOA(rxb0_wbdat),
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.ADDRA({wb_adr_i[8:0], 5'd0}),
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.WEA({4{wb_en & wb_we_i & (wb_buf == 2'b00)}} & wb_sel_i_le),
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.ENA(1'b1),
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.RSTA(1'b0),
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.CLKA(sys_clk),
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.DIB(rxb0_dat),
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.DIPB(1'd0),
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.DOB(),
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.ADDRB({rxb0_adr, 3'd0}),
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.WEB({4{rxb0_we}}),
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.ENB(1'b1),
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.RSTB(1'b0),
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.CLKB(phy_rx_clk)
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);
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wire [31:0] rxb1_wbdat;
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RAMB16BWER #(
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.DATA_WIDTH_A(36),
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.DATA_WIDTH_B(9),
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.DOA_REG(0),
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.DOB_REG(0),
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.EN_RSTRAM_A("FALSE"),
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.EN_RSTRAM_B("FALSE"),
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.SIM_DEVICE("SPARTAN6"),
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.WRITE_MODE_A("WRITE_FIRST"),
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.WRITE_MODE_B("WRITE_FIRST")
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) rxb1 (
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.DIA(wb_dat_i_le),
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.DIPA(4'd0),
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.DOA(rxb1_wbdat),
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.ADDRA({wb_adr_i[8:0], 5'd0}),
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.WEA({4{wb_en & wb_we_i & (wb_buf == 2'b01)}} & wb_sel_i_le),
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.ENA(1'b1),
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.RSTA(1'b0),
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.CLKA(sys_clk),
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.DIB(rxb1_dat),
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.DIPB(1'd0),
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.DOB(),
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.ADDRB({rxb1_adr, 3'd0}),
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.WEB({4{rxb1_we}}),
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.ENB(1'b1),
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.RSTB(1'b0),
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.CLKB(phy_rx_clk)
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);
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wire [31:0] txb_wbdat;
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RAMB16BWER #(
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.DATA_WIDTH_A(36),
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.DATA_WIDTH_B(9),
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.DOA_REG(0),
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.DOB_REG(0),
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.EN_RSTRAM_A("FALSE"),
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.EN_RSTRAM_B("FALSE"),
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.SIM_DEVICE("SPARTAN6"),
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.WRITE_MODE_A("WRITE_FIRST"),
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.WRITE_MODE_B("WRITE_FIRST")
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) txb (
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.DIA(wb_dat_i_le),
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.DIPA(4'd0),
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.DOA(txb_wbdat),
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.ADDRA({wb_adr_i[8:0], 5'd0}),
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.WEA({4{wb_en & wb_we_i & (wb_buf == 2'b10)}} & wb_sel_i_le),
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.ENA(1'b1),
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.RSTA(1'b0),
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.CLKA(sys_clk),
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.DIB(8'd0),
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.DIPB(1'd0),
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.DOB(txb_dat),
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.ADDRB({txb_adr, 3'd0}),
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.WEB(4'd0),
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.ENB(1'b1),
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.RSTB(1'b0),
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.CLKB(phy_tx_clk)
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);
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always @(posedge sys_clk) begin
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if(sys_rst)
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wb_ack_o <= 1'b0;
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else begin
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wb_ack_o <= 1'b0;
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if(wb_en & ~wb_ack_o)
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wb_ack_o <= 1'b1;
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end
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end
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reg [1:0] wb_buf_r;
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always @(posedge sys_clk)
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wb_buf_r <= wb_buf;
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reg [31:0] wb_dat_o_le;
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always @(*) begin
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case(wb_buf_r)
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2'b00: wb_dat_o_le = rxb0_wbdat;
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2'b01: wb_dat_o_le = rxb1_wbdat;
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default: wb_dat_o_le = txb_wbdat;
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endcase
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end
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assign wb_dat_o = {wb_dat_o_le[7:0], wb_dat_o_le[15:8], wb_dat_o_le[23:16], wb_dat_o_le[31:24]};
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endmodule
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