104 lines
3.1 KiB
Python
104 lines
3.1 KiB
Python
#
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# This file is part of LiteX.
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#
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# Copyright (c) 2022-2023 MoTeC
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# Copyright (c) 2022-2023 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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import unittest
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import random
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from migen import *
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from litex.gen.sim import *
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from litex.soc.cores.spi.spi_mmap import SPIMaster
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class TestSPIMMAP(unittest.TestCase):
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def test_spi_master(self):
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pads = Record([("clk", 1), ("cs_n", 4), ("mosi", 1), ("miso", 1)])
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dut = SPIMaster(pads=pads, data_width=32, sys_clk_freq=int(100e6))
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def generator(dut):
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data = [
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0x12345678,
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0xdeadbeef,
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]
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#data = [
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# 0x80000001,
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# 0x80000001,
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#]
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# Config: Mode0, Loopback, Sys-Clk/4
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yield dut.loopback.eq(1)
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yield dut.clk_divider.eq(4)
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yield dut.mode.eq(0)
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yield
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yield dut.mosi.eq(data[0])
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yield dut.cs.eq(0b0001)
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yield dut.length.eq(32)
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yield dut.start.eq(1)
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yield
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yield dut.start.eq(0)
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while (yield dut.done) == 0b0:
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yield
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yield dut.cs.eq(0b0000)
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for i in range(16):
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yield
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print(f"mosi_data : {(yield dut.miso):08x}")
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# Config: Mode3, Loopback, Sys-Clk/4.
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yield dut.loopback.eq(1)
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yield dut.clk_divider.eq(4)
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yield dut.mode.eq(3)
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yield
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yield dut.mosi.eq(data[0])
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yield dut.cs.eq(0b0001)
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yield dut.length.eq(32)
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yield dut.start.eq(1)
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yield
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yield dut.start.eq(0)
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while (yield dut.done) == 0b0:
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yield
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yield dut.cs.eq(0b0000)
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for i in range(16):
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yield
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print(f"mosi_data : {(yield dut.miso):08x}")
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# Config: Mode0, Loopback, Sys-Clk/8.
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yield dut.loopback.eq(1)
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yield dut.clk_divider.eq(8)
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yield dut.mode.eq(0)
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yield
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yield dut.mosi.eq(data[1])
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yield dut.cs.eq(0b0001)
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yield dut.length.eq(32)
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yield dut.start.eq(1)
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yield
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yield dut.start.eq(0)
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while (yield dut.done) == 0b0:
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yield
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yield dut.cs.eq(0b0000)
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for i in range(16):
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yield
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print(f"mosi_data : {(yield dut.miso):08x}")
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# Config: Mode3, Loopback, Sys-Clk/8.
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yield dut.loopback.eq(1)
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yield dut.clk_divider.eq(8)
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yield dut.mode.eq(3)
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yield
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yield dut.mosi.eq(data[1])
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yield dut.cs.eq(0b0001)
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yield dut.length.eq(32)
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yield dut.start.eq(1)
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yield
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yield dut.start.eq(0)
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while (yield dut.done) == 0b0:
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yield
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yield dut.cs.eq(0b0000)
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for i in range(16):
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yield
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print(f"mosi_data : {(yield dut.miso):08x}")
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run_simulation(dut, generator(dut), vcd_name="sim.vcd")
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