litex/migen/bank
2012-02-06 16:15:27 +01:00
..
__init__.py Cleanup 2011-12-05 19:25:32 +01:00
csrgen.py bank: support registers larger than the bus word width 2012-02-06 16:15:27 +01:00
description.py bank: support registers larger than the bus word width 2012-02-06 16:15:27 +01:00