70 lines
1.5 KiB
Python
70 lines
1.5 KiB
Python
from misoclib.com.liteeth.common import *
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from misoclib.com.liteeth.generic import *
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from migen.bus import wishbone
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class LiteEthEtherboneWishboneMaster(Module):
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def __init__(self):
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self.sink = sink = Sink(eth_etherbone_mmap_description(32))
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self.source = source = Source(eth_etherbone_mmap_description(32))
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self.bus = bus = wishbone.Interface()
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###s
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self.submodules.data = data = FlipFlop(32)
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self.comb += data.d.eq(bus.dat_r)
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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sink.ack.eq(1),
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If(sink.stb & sink.sop,
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sink.ack.eq(0),
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If(sink.we,
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NextState("WRITE_DATA")
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).Else(
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NextState("READ_DATA")
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)
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)
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)
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fsm.act("WRITE_DATA",
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bus.adr.eq(sink.addr),
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bus.dat_w.eq(sink.data),
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bus.sel.eq(sink.be),
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bus.stb.eq(sink.stb),
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bus.we.eq(1),
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bus.cyc.eq(1),
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If(bus.stb & bus.ack,
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sink.ack.eq(1),
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If(sink.eop,
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NextState("IDLE")
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)
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)
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)
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fsm.act("READ_DATA",
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bus.adr.eq(sink.addr),
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bus.sel.eq(sink.be),
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bus.stb.eq(sink.stb),
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bus.cyc.eq(1),
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If(bus.stb & bus.ack,
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data.ce.eq(1),
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NextState("SEND_DATA")
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)
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)
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fsm.act("SEND_DATA",
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source.stb.eq(sink.stb),
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source.sop.eq(sink.sop),
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source.eop.eq(sink.eop),
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source.base_addr.eq(sink.base_addr),
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source.addr.eq(sink.addr),
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source.count.eq(sink.count),
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source.be.eq(sink.be),
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source.we.eq(1),
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source.data.eq(data.q),
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If(source.stb & source.ack,
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sink.ack.eq(1),
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If(source.eop,
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NextState("IDLE")
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).Else(
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NextState("READ_DATA")
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)
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)
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)
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