86 lines
2.2 KiB
Python
86 lines
2.2 KiB
Python
from random import Random
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from migen.fhdl import verilog
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from migen.flow.ala import *
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from migen.flow.network import *
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from migen.actorlib import dma_wishbone
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from migen.actorlib.sim import *
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from migen.bus import wishbone, asmibus
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from migen.sim.generic import Simulator
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from migen.sim.icarus import Runner
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class MyModel:
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def read(self, address):
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return address + 4
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class MyModelWB(MyModel, wishbone.TargetModel):
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def __init__(self):
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self.prng = Random(763627)
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def can_ack(self, bus):
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return self.prng.randrange(0, 2)
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class MyModelASMI(MyModel, asmibus.TargetModel):
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pass
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def adrgen_gen():
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for i in range(10):
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print("Address: " + str(i))
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yield Token("address", {"a": i})
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def dumper_gen():
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while True:
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t = Token("data")
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yield t
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print("Received: " + str(t.value["d"]))
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def trgen_gen():
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for i in range(10):
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a = i
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d = i+10
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print("Address: " + str(a) + " Data: " + str(d))
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yield Token("address_data", {"a": a, "d": d})
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def wishbone_sim(efragment, master, end_simulation):
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peripheral = wishbone.Target(MyModelWB())
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tap = wishbone.Tap(peripheral.bus)
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interconnect = wishbone.InterconnectPointToPoint(master.bus, peripheral.bus)
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fragment = efragment \
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+ peripheral.get_fragment() \
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+ tap.get_fragment() \
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+ interconnect.get_fragment() \
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+ Fragment(sim=[end_simulation])
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sim = Simulator(fragment, Runner())
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sim.run()
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def test_wb_reader():
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print("*** Testing Wishbone reader")
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adrgen = SimActor(adrgen_gen(), ("address", Source, [("a", BV(30))]))
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reader = dma_wishbone.Reader()
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dumper = SimActor(dumper_gen(), ("data", Sink, [("d", BV(32))]))
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g = DataFlowGraph()
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g.add_connection(adrgen, reader)
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g.add_connection(reader, dumper)
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comp = CompositeActor(g)
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def end_simulation(s):
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s.interrupt = adrgen.done and not s.rd(comp.busy)
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wishbone_sim(comp.get_fragment(), reader, end_simulation)
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def test_wb_writer():
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print("*** Testing Wishbone writer")
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trgen = SimActor(trgen_gen(), ("address_data", Source, [("a", BV(30)), ("d", BV(32))]))
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writer = dma_wishbone.Writer()
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g = DataFlowGraph()
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g.add_connection(trgen, writer)
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comp = CompositeActor(g)
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def end_simulation(s):
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s.interrupt = trgen.done and not s.rd(comp.busy)
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wishbone_sim(comp.get_fragment(), writer, end_simulation)
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test_wb_reader()
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test_wb_writer()
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