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52 lines
1.6 KiB
Python
52 lines
1.6 KiB
Python
from migen.fhdl.structure import *
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from migen.fhdl.module import Module
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from migen.flow.network import *
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from migen.bank.description import CSRStorage
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from migen.actorlib import dma_asmi, structuring, sim, spi
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from milkymist.framebuffer.lib import bpp, pixel_layout, dac_layout, FrameInitiator, VTG, FIFO
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class Framebuffer(Module):
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def __init__(self, pads, asmiport, simulation=False):
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pack_factor = asmiport.hub.dw//(2*bpp)
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packed_pixels = structuring.pack_layout(pixel_layout, pack_factor)
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fi = FrameInitiator()
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dma = spi.DMAReadController(dma_asmi.Reader(asmiport), spi.MODE_EXTERNAL, length_reset=640*480*4)
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cast = structuring.Cast(asmiport.hub.dw, packed_pixels, reverse_to=True)
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unpack = structuring.Unpack(pack_factor, pixel_layout)
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vtg = VTG()
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if simulation:
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fifo = sim.SimActor(sim_fifo_gen(), ("dac", Sink, dac_layout))
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else:
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fifo = FIFO()
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g = DataFlowGraph()
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g.add_connection(fi, vtg, sink_ep="timing")
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g.add_connection(dma, cast)
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g.add_connection(cast, unpack)
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g.add_connection(unpack, vtg, sink_ep="pixels")
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g.add_connection(vtg, fifo)
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self.submodules += CompositeActor(g)
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self._enable = CSRStorage()
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self.comb += [
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fi.trigger.eq(self._enable.storage),
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dma.generator.trigger.eq(self._enable.storage),
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]
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self._fi = fi
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self._dma = dma
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# Drive pads
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if not simulation:
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self.comb += [
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pads.hsync_n.eq(fifo.vga_hsync_n),
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pads.vsync_n.eq(fifo.vga_vsync_n),
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pads.r.eq(fifo.vga_r),
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pads.g.eq(fifo.vga_g),
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pads.b.eq(fifo.vga_b)
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]
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self.comb += pads.psave_n.eq(1)
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def get_csrs(self):
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return [self._enable] + self._fi.get_csrs() + self._dma.get_csrs()
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