215 lines
4.9 KiB
Coq
215 lines
4.9 KiB
Coq
/*
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* Milkymist SoC
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* Copyright (C) 2007, 2008, 2009, 2011 Sebastien Bourdeauducq
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, version 3 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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module tb_conbus();
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reg sys_rst;
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reg sys_clk;
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//------------------------------------------------------------------
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// Wishbone master wires
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//------------------------------------------------------------------
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wire [31:0] wishbone_m1_adr,
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wishbone_m2_adr;
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wire [31:0] wishbone_m1_dat_r,
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wishbone_m1_dat_w,
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wishbone_m2_dat_r,
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wishbone_m2_dat_w;
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wire [3:0] wishbone_m1_sel,
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wishbone_m2_sel;
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wire wishbone_m1_we,
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wishbone_m2_we;
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wire wishbone_m1_cyc,
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wishbone_m2_cyc;
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wire wishbone_m1_stb,
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wishbone_m2_stb;
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wire wishbone_m1_ack,
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wishbone_m2_ack;
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//------------------------------------------------------------------
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// Wishbone slave wires
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//------------------------------------------------------------------
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wire [31:0] wishbone_s1_adr,
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wishbone_s2_adr;
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wire [31:0] wishbone_s1_dat_r,
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wishbone_s1_dat_w,
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wishbone_s2_dat_r,
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wishbone_s2_dat_w;
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wire [3:0] wishbone_s1_sel,
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wishbone_s2_sel;
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wire wishbone_s1_we,
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wishbone_s2_we;
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wire wishbone_s1_cyc,
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wishbone_s2_cyc;
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wire wishbone_s1_stb,
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wishbone_s2_stb;
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wire wishbone_s1_ack,
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wishbone_s2_ack;
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//---------------------------------------------------------------------------
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// Wishbone switch
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//---------------------------------------------------------------------------
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intercon dut(
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.sys_clk(sys_clk),
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.sys_rst(sys_rst),
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// Master 0
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.wishbone_m1_dat_o(wishbone_m1_dat_w),
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.wishbone_m1_dat_i(wishbone_m1_dat_r),
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.wishbone_m1_adr_o(wishbone_m1_adr),
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.wishbone_m1_we_o(wishbone_m1_we),
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.wishbone_m1_sel_o(wishbone_m1_sel),
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.wishbone_m1_cyc_o(wishbone_m1_cyc),
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.wishbone_m1_stb_o(wishbone_m1_stb),
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.wishbone_m1_ack_i(wishbone_m1_ack),
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// Master 1
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.wishbone_m2_dat_o(wishbone_m2_dat_w),
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.wishbone_m2_dat_i(wishbone_m2_dat_r),
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.wishbone_m2_adr_o(wishbone_m2_adr),
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.wishbone_m2_we_o(wishbone_m2_we),
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.wishbone_m2_sel_o(wishbone_m2_sel),
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.wishbone_m2_cyc_o(wishbone_m2_cyc),
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.wishbone_m2_stb_o(wishbone_m2_stb),
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.wishbone_m2_ack_i(wishbone_m2_ack),
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// Slave 0
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.wishbone_s1_dat_o(wishbone_s1_dat_r),
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.wishbone_s1_dat_i(wishbone_s1_dat_w),
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.wishbone_s1_adr_i(wishbone_s1_adr),
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.wishbone_s1_sel_i(wishbone_s1_sel),
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.wishbone_s1_we_i(wishbone_s1_we),
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.wishbone_s1_cyc_i(wishbone_s1_cyc),
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.wishbone_s1_stb_i(wishbone_s1_stb),
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.wishbone_s1_ack_o(wishbone_s1_ack),
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// Slave 1
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.wishbone_s2_dat_o(wishbone_s2_dat_r),
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.wishbone_s2_dat_i(wishbone_s2_dat_w),
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.wishbone_s2_adr_i(wishbone_s2_adr),
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.wishbone_s2_sel_i(wishbone_s2_sel),
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.wishbone_s2_we_i(wishbone_s2_we),
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.wishbone_s2_cyc_i(wishbone_s2_cyc),
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.wishbone_s2_stb_i(wishbone_s2_stb),
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.wishbone_s2_ack_o(wishbone_s2_ack)
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);
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//---------------------------------------------------------------------------
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// Masters
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//---------------------------------------------------------------------------
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wire wishbone_m1_end;
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master #(
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.id(0)
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) m0 (
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.sys_clk(sys_clk),
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.sys_rst(sys_rst),
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.dat_w(wishbone_m1_dat_w),
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.dat_r(wishbone_m1_dat_r),
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.adr(wishbone_m1_adr),
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.we(wishbone_m1_we),
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.sel(wishbone_m1_sel),
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.cyc(wishbone_m1_cyc),
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.stb(wishbone_m1_stb),
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.ack(wishbone_m1_ack),
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.tend(wishbone_m1_end)
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);
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wire wishbone_m2_end;
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master #(
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.id(1)
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) m1 (
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.sys_clk(sys_clk),
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.sys_rst(sys_rst),
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.dat_w(wishbone_m2_dat_w),
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.dat_r(wishbone_m2_dat_r),
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.adr(wishbone_m2_adr),
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.we(wishbone_m2_we),
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.sel(wishbone_m2_sel),
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.cyc(wishbone_m2_cyc),
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.stb(wishbone_m2_stb),
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.ack(wishbone_m2_ack),
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.tend(wishbone_m2_end)
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);
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//---------------------------------------------------------------------------
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// Slaves
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//---------------------------------------------------------------------------
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slave #(
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.id(0)
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) s0 (
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.sys_clk(sys_clk),
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.sys_rst(sys_rst),
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.dat_w(wishbone_s1_dat_w),
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.dat_r(wishbone_s1_dat_r),
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.adr(wishbone_s1_adr),
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.we(wishbone_s1_we),
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.sel(wishbone_s1_sel),
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.cyc(wishbone_s1_cyc),
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.stb(wishbone_s1_stb),
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.ack(wishbone_s1_ack)
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);
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slave #(
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.id(1)
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) s1 (
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.sys_clk(sys_clk),
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.sys_rst(sys_rst),
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.dat_w(wishbone_s2_dat_w),
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.dat_r(wishbone_s2_dat_r),
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.adr(wishbone_s2_adr),
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.we(wishbone_s2_we),
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.sel(wishbone_s2_sel),
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.cyc(wishbone_s2_cyc),
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.stb(wishbone_s2_stb),
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.ack(wishbone_s2_ack)
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);
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initial sys_clk = 1'b0;
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always #5 sys_clk = ~sys_clk;
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wire all_end = wishbone_m1_end & wishbone_m2_end;
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always begin
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$dumpfile("intercon.vcd");
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$dumpvars(1, dut);
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sys_rst = 1'b1;
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@(posedge sys_clk);
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#1 sys_rst = 1'b0;
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@(posedge all_end);
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$finish;
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end
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endmodule
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