154 lines
6.0 KiB
Python
154 lines
6.0 KiB
Python
#
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# This file is part of LiteX.
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#
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# Copyright (c) 2020 Pepijn de Vos <pepijndevos@gmail.com>
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# Copyright (c) 2015-2018 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import sys
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import math
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import subprocess
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from shutil import which, copyfile
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from migen.fhdl.structure import _Fragment
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from litex.build.generic_toolchain import GenericToolchain
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from litex.build.generic_platform import *
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from litex.build import tools
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# GowinToolchain -----------------------------------------------------------------------------------
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class GowinToolchain(GenericToolchain):
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attr_translate = {}
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def __init__(self):
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super().__init__()
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self.options = {}
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def finalize(self):
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if self.platform.verilog_include_paths:
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self.options["include_path"] = "{" + ";".join(self.platform.verilog_include_paths) + "}"
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self.apply_hyperram_integration_hack(self._build_name + ".v")
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def apply_hyperram_integration_hack(self, v_file):
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# FIXME: Gowin EDA expects a very specific HypeRAM integration pattern, modify generated verilog to match it.
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# Convert to vectors.
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tools.replace_in_file(v_file, "O_hpram_reset_n", "O_hpram_reset_n[0]")
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tools.replace_in_file(v_file, "O_hpram_cs_n", "O_hpram_cs_n[0]")
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tools.replace_in_file(v_file, "O_hpram_rwds", "O_hpram_rwds[0]")
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tools.replace_in_file(v_file, "O_hpram_ck ", "O_hpram_ck[0] ")
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tools.replace_in_file(v_file, "O_hpram_ck_n ", "O_hpram_ck_n[0] ")
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tools.replace_in_file(v_file, "O_hpram_ck,", "O_hpram_ck[0],")
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tools.replace_in_file(v_file, "O_hpram_ck_n,", "O_hpram_ck_n[0],")
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tools.replace_in_file(v_file, "wire O_hpram_reset_n[0]", "wire [0:0] O_hpram_reset_n")
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tools.replace_in_file(v_file, "wire O_hpram_cs_n[0]", "wire [0:0] O_hpram_cs_n")
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tools.replace_in_file(v_file, "wire IO_hpram_rwds[0]", "wire [0:0] IO_hpram_rwds")
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tools.replace_in_file(v_file, "wire O_hpram_ck[0]", "wire [0:0] O_hpram_ck")
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tools.replace_in_file(v_file, "wire O_hpram_ck_n[0]", "wire [0:0] O_hpram_ck_n")
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# Apply Synthesis directives.
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tools.replace_in_file(v_file, "wire [0:0] IO_hpram_rwds,", "wire [0:0] IO_hpram_rwds, /* synthesis syn_tristate = 1 */")
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tools.replace_in_file(v_file, "wire [7:0] IO_hpram_dq,", "wire [7:0] IO_hpram_dq, /* synthesis syn_tristate = 1 */")
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tools.replace_in_file(v_file, "[1:0] IO_psram_rwds,", "[1:0] IO_psram_rwds, /* synthesis syn_tristate = 1 */")
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tools.replace_in_file(v_file, "[15:0] IO_psram_dq,", "[15:0] IO_psram_dq, /* synthesis syn_tristate = 1 */")
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# Constraints (.cst ) --------------------------------------------------------------------------
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def build_io_constraints(self):
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cst = []
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flat_sc = []
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for name, pins, other, resource in self.named_sc:
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if len(pins) > 1:
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for i, p in enumerate(pins):
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flat_sc.append((f"{name}[{i}]", p, other))
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else:
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flat_sc.append((name, pins[0], other))
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for name, pin, other in flat_sc:
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if pin != "X":
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cst.append(f"IO_LOC \"{name}\" {pin};")
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for c in other:
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if isinstance(c, IOStandard):
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cst.append(f"IO_PORT \"{name}\" IO_TYPE={c.name};")
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elif isinstance(c, Misc):
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cst.append(f"IO_PORT \"{name}\" {c.misc};")
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if self.named_pc:
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cst.extend(self.named_pc)
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tools.write_to_file(f"{self._build_name}.cst", "\n".join(cst))
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return (f"{self._build_name}.cst", "CST")
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# Timing Constraints (.sdc ) -------------------------------------------------------------------
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def build_timing_constraints(self, vns):
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sdc = []
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for clk, period in sorted(self.clocks.items(), key=lambda x: x[0].duid):
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sdc.append(f"create_clock -name {vns.get_name(clk)} -period {str(period)} [get_ports {{{vns.get_name(clk)}}}]")
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tools.write_to_file(f"{self._build_name}.sdc", "\n".join(sdc))
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return (f"{self._build_name}.sdc", "SDC")
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# Project (tcl) --------------------------------------------------------------------------------
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def build_project(self):
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tcl = []
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# Set Device.
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tcl.append(f"set_device -name {self.platform.devicename} {self.platform.device}")
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# Add IOs Constraints.
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tcl.append(f"add_file {self._build_name}.cst")
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# Add Timings Constraints.
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tcl.append(f"add_file {self._build_name}.sdc")
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# Add Sources.
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for f, typ, lib in self.platform.sources:
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# Support windows/powershell
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if sys.platform == "win32":
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f = f.replace("\\", "\\\\")
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tcl.append(f"add_file {f}")
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# Set Options.
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for opt, val in self.options.items():
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tcl.append(f"set_option -{opt} {val}")
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# Run.
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tcl.append("run all")
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# Generate .tcl.
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tools.write_to_file("run.tcl", "\n".join(tcl))
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# Script ---------------------------------------------------------------------------------------
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def build_script(self):
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return "" # gw_sh use
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def run_script(self, script):
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# Support Powershell/WSL platform
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# Some python distros for windows (e.g, oss-cad-suite)
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# which does not have 'os.uname' support, we should check 'sys.platform' firstly.
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gw_sh = "gw_sh"
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if sys.platform.find("linux") >= 0:
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if os.uname().release.find("WSL") > 0:
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gw_sh += ".exe"
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if which(gw_sh) is None:
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msg = "Unable to find Gowin toolchain, please:\n"
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msg += "- Add Gowin toolchain to your $PATH."
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raise OSError(msg)
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if subprocess.call([gw_sh, "run.tcl"]) != 0:
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raise OSError("Error occured during Gowin's script execution.")
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# Copy Bitstream to from impl to gateware directory.
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copyfile(
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os.path.join("impl", "pnr", "project.fs"),
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os.path.join(self._build_name + ".fs")
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)
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