Gwenhael Goavec-Merou 3da470048a build/gowin/apicula: append _synth_opts with specific requirements according to FPGA model		2024-09-01 09:53:24 +02:00
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build	build/gowin/apicula: append _synth_opts with specific requirements according to FPGA model	2024-09-01 09:53:24 +02:00
compat	compat/soc_core: Fix register_mem/rom missing imports.	2022-11-09 19:11:15 +01:00
gen	gen/fhdl/hierarchy: Sort instances to generate deterministic hierarchy in verilog.	2024-07-03 21:44:31 +02:00
soc	Merge pull request #2053 from enjoy-digital/hyperram_new	2024-08-30 15:38:59 +02:00
tools	json2dts_zephyr: omit disable handler	2024-08-20 11:23:21 +02:00
__init__.py	get_data_mod(): fix recursive exception reporting	2024-04-22 12:09:45 +10:00