229 lines
6.6 KiB
Python
229 lines
6.6 KiB
Python
import os
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from migen.fhdl.std import *
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from migen.bank import csrgen
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from migen.bus import wishbone, csr
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from migen.bus import wishbone2csr
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.bank.description import *
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from miscope import MiLa, Term, UART2Wishbone
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from miscope.uart2wishbone import UART2Wishbone
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from misoclib import identifier
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from lib.sata.common import *
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from lib.sata.phy import SATAPHY
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from lib.sata import SATACON
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from lib.sata.bist import SATABIST
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from migen.genlib.cdc import *
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class _CRG(Module):
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def __init__(self, platform):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_por = ClockDomain(reset_less=True)
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clk200 = platform.request("clk200")
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clk200_se = Signal()
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self.specials += Instance("IBUFDS", i_I=clk200.p, i_IB=clk200.n, o_O=clk200_se)
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pll_locked = Signal()
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pll_fb = Signal()
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pll_sys = Signal()
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self.specials += [
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Instance("PLLE2_BASE",
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p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
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# VCO @ 1GHz
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p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=5.0,
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p_CLKFBOUT_MULT=5, p_DIVCLK_DIVIDE=1,
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i_CLKIN1=clk200_se, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
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# 100MHz
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p_CLKOUT0_DIVIDE=10, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=pll_sys,
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p_CLKOUT1_DIVIDE=2, p_CLKOUT1_PHASE=0.0, #o_CLKOUT1=,
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p_CLKOUT2_DIVIDE=2, p_CLKOUT2_PHASE=0.0, #o_CLKOUT2=,
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p_CLKOUT3_DIVIDE=2, p_CLKOUT3_PHASE=0.0, #o_CLKOUT3=,
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p_CLKOUT4_DIVIDE=2, p_CLKOUT4_PHASE=0.0, #o_CLKOUT4=
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),
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Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk),
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AsyncResetSynchronizer(self.cd_sys, ~pll_locked | platform.request("cpu_reset")),
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]
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class UART2WB(Module):
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csr_base = 0x00000000
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csr_data_width = 8
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csr_map = {
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"uart2wb": 0,
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"identifier": 2,
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}
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interrupt_map = {}
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cpu_type = None
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def __init__(self, platform, clk_freq):
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self.uart2wb = UART2Wishbone(platform.request("serial"), clk_freq, baud=921600)
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# CSR bridge 0x00000000 (shadow @0x00000000)
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self.wishbone2csr = wishbone2csr.WB2CSR(bus_csr=csr.Interface(self.csr_data_width))
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self._wb_masters = [self.uart2wb.wishbone]
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self._wb_slaves = [(lambda a: a[23:25] == 0, self.wishbone2csr.wishbone)]
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self.cpu_csr_regions = [] # list of (name, origin, busword, csr_list/Memory)
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# CSR
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self.identifier = identifier.Identifier(0, int(clk_freq), 0)
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def add_wb_master(self, wbm):
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if self.finalized:
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raise FinalizeError
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self._wb_masters.append(wbm)
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def add_wb_slave(self, address_decoder, interface):
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if self.finalized:
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raise FinalizeError
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self._wb_slaves.append((address_decoder, interface))
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def add_cpu_memory_region(self, name, origin, length):
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self.cpu_memory_regions.append((name, origin, length))
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def add_cpu_csr_region(self, name, origin, busword, obj):
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self.cpu_csr_regions.append((name, origin, busword, obj))
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def do_finalize(self):
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# Wishbone
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self.wishbonecon = wishbone.InterconnectShared(self._wb_masters,
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self._wb_slaves, register=True)
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# CSR
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self.csrbankarray = csrgen.BankArray(self,
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lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override],
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data_width=self.csr_data_width)
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self.csrcon = csr.Interconnect(self.wishbone2csr.csr, self.csrbankarray.get_buses())
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for name, csrs, mapaddr, rmap in self.csrbankarray.banks:
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self.add_cpu_csr_region(name, 0xe0000000+0x800*mapaddr, flen(rmap.bus.dat_w), csrs)
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for name, memory, mapaddr, mmap in self.csrbankarray.srams:
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self.add_cpu_csr_region(name, 0xe0000000+0x800*mapaddr, flen(rmap.bus.dat_w), memory)
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class SimDesign(UART2WB):
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default_platform = "kc705"
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def __init__(self, platform, export_mila=False):
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clk_freq = 100*1000000
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UART2WB.__init__(self, platform, clk_freq)
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self.crg = _CRG(platform)
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self.sata_phy_host = SATAPHY(platform.request("sata_host"), clk_freq, host=True)
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self.comb += [
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self.sata_phy_host.sink.stb.eq(1),
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self.sata_phy_host.sink.data.eq(primitives["SYNC"]),
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self.sata_phy_host.sink.charisk.eq(0b0001)
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]
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self.sata_phy_device = SATAPHY(platform.request("sata_device"), clk_freq, host=False)
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self.comb += [
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self.sata_phy_device.sink.stb.eq(1),
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self.sata_phy_device.sink.data.eq(primitives["SYNC"]),
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self.sata_phy_device.sink.charisk.eq(0b0001)
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]
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class ClockLeds(Module):
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def __init__(self, platform):
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led_sata_rx = platform.request("user_led", 0)
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led_sata_tx = platform.request("user_led", 1)
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sata_rx_cnt = Signal(32)
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sata_tx_cnt = Signal(32)
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self.sync.sata_rx += \
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If(sata_rx_cnt == 0,
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led_sata_rx.eq(~led_sata_rx),
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sata_rx_cnt.eq(150*1000*1000//2)
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).Else(
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sata_rx_cnt.eq(sata_rx_cnt-1)
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)
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self.sync.sata_tx += \
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If(sata_tx_cnt == 0,
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led_sata_tx.eq(~led_sata_tx),
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sata_tx_cnt.eq(150*1000*1000//2)
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).Else(
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sata_tx_cnt.eq(sata_tx_cnt-1)
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)
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class TestDesign(UART2WB, AutoCSR):
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default_platform = "kc705"
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csr_map = {
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"mila": 10,
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"command_generator": 11,
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"bist": 12
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}
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csr_map.update(UART2WB.csr_map)
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def __init__(self, platform, export_mila=False):
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clk_freq = 100*1000000
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UART2WB.__init__(self, platform, clk_freq)
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self.crg = _CRG(platform)
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self.sata_phy = SATAPHY(platform.request("sata_host"), clk_freq, host=True, speed="SATA2")
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self.sata_con = SATACON(self.sata_phy, sector_size=512, max_count=8)
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self.bist = SATABIST(self.sata_con)
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self.clock_leds = ClockLeds(platform)
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self.comb += platform.request("user_led", 2).eq(self.sata_phy.crg.ready)
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self.comb += platform.request("user_led", 3).eq(self.sata_phy.ctrl.ready)
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ctrl = self.sata_phy.ctrl
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self.command_tx_fsm_state = Signal(4)
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self.transport_tx_fsm_state = Signal(4)
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self.link_tx_fsm_state = Signal(4)
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self.command_rx_fsm_state = Signal(4)
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self.command_rx_out_fsm_state = Signal(4)
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self.transport_rx_fsm_state = Signal(4)
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self.link_rx_fsm_state = Signal(4)
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debug = (
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ctrl.ready,
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ctrl.sink.data,
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ctrl.sink.charisk,
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self.sata_phy.source.stb,
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self.sata_phy.source.data,
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self.sata_phy.source.charisk,
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self.sata_phy.sink.stb,
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self.sata_phy.sink.data,
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self.sata_phy.sink.charisk,
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self.sata_con.sink.stb,
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self.sata_con.sink.sop,
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self.sata_con.sink.eop,
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self.sata_con.sink.ack,
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self.sata_con.sink.write,
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self.sata_con.sink.read,
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self.sata_con.source.stb,
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self.sata_con.source.sop,
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self.sata_con.source.eop,
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self.sata_con.source.ack,
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self.sata_con.source.write,
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self.sata_con.source.read,
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self.sata_con.source.success,
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self.sata_con.source.failed,
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self.sata_con.source.data
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)
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self.mila = MiLa(depth=2048, dat=Cat(*debug))
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self.mila.add_port(Term)
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if export_mila:
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mila_filename = os.path.join(platform.soc_ext_path, "test", "mila.csv")
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self.mila.export(self, debug, mila_filename)
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#default_subtarget = SimDesign
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default_subtarget = TestDesign |